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Figure No.
6-4
Single Transfer Example 3 ...........................................................................................................................225
6-5
Single Transfer Example 4 ...........................................................................................................................225
6-6
Single-Step Transfer Example 1...................................................................................................................226
6-7
Single-Step Transfer Example 2...................................................................................................................226
6-8
Block Transfer Example ...............................................................................................................................227
6-9
Timing of Access to SRAM, External ROM, and External I/O During 2-Cycle DMA Transfer.......................229
Timing of 2-Cycle DMA Transfer (External I/O → SRAM) ............................................................................231
6-10
Timing of 2-Cycle DMA Transfer (SRAM → EDO DRAM) ............................................................................232
6-11
Timing of 2-Cycle DMA Transfer (EDO DRAM → SRAM) ............................................................................235
6-12
Timing of 2-Cycle DMA Transfer (SRAM → SDRAM) ..................................................................................238
6-13
Timing of 2-Cycle DMA Transfer (SDRAM → SRAM) ..................................................................................241
6-14
6-15
Circuit Example When Flyby Transfer Is Performed Between External I/O and SRAM................................244
Timing of Flyby Transfer (DRAM → External I/O).........................................................................................245
6-16
6-17
Timing of Access to SRAM, External ROM, and External I/O During DMA Flyby Transfer ..........................248
6-18
Page ROM Access Timing During DMA Flyby Transfer ...............................................................................250
6-19
DRAM Access Timing During DMA Flyby Transfer ......................................................................................251
6-20
Buffer Register Configuration .......................................................................................................................257
6-21
Terminal Count Signal (TCn) Timing Example .............................................................................................259
6-22
Example of Forcible Interrupt of DMA Transfer ............................................................................................259
6-23
Example of Forcible Termination of DMA Transfer.......................................................................................260
6-24
Time to Perform Single Transfer One Time..................................................................................................262
7-1
Servicing Configuration of Non-Maskable Interrupt ......................................................................................268
7-2
Acknowledging Non-Maskable Interrupt Request.........................................................................................269
7-3
RETI Instruction Processing .........................................................................................................................270
7-4
Maskable Interrupt Servicing ........................................................................................................................273
7-5
RETI Instruction Processing .........................................................................................................................274
7-6
Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is
Being Serviced .............................................................................................................................................276
7-7
Example of Servicing Interrupt Requests Simultaneously Generated ..........................................................278
7-8
Software Exception Processing....................................................................................................................288
7-9
RETI Instruction Processing .........................................................................................................................289
7-10
Exception Trap Processing...........................................................................................................................292
7-11
Restore Processing from Exception Trap .....................................................................................................292
7-12
Debug Trap Processing................................................................................................................................293
7-13
Restore Processing from Debug Trap ..........................................................................................................294
7-14
Pipeline Operation at Interrupt Request Acknowledgement (Outline) ..........................................................297
LIST OF FIGURES (2/5)
Title
User's Manual U14359EJ4V0UM
Page
21
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