NEC V850E/MA1 User Manual page 136

(2) SDRAM (when read, latency = 2, three idle states inserted)
SDCLK (output)
HLDRQ (input)
HLDAK (output)
Note 4 (output)
Bank address (output)
A10 (output)
A0 to A9 (output)
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
D0 to D15 (I/O)
SDCKE (output)
H
Notes 1. This idle state (TI) is inserted by means of a BCC register setting.
2. This idle state (TI) is independent of the BCC register setting.
3. The all bank precharge command is always executed.
4. Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The circle
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
136
CHAPTER 4 BUS CONTROL FUNCTION
TW TACT TBCW TREAD TLATE TLATE
BCW
Address
Bank
Address
address
Row
Address
address
Row
Address
address
indicates the sampling timing.
User's Manual U14359EJ4V0UM
Note 1 Note 1 Note 1 Note 2
TI TI TI TI
Column address
Data
Note 2 Note 3
TH TH TI TW TPRE
Undefined
Undefined
Undefined
Undefined