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14.3.10 Port DL
Port DL (PDL) is a 16-bit I/O port that can be set in the input or output mode in 1-bit units.
When the higher 8 bits of port DL are used as port DLH (PDLH), and the lower 8 bits as port DLL (PDLL), port DL
becomes two 8-bit ports that can be set in the input or output mode in 1-bit units.
15
14
PDL
PDL15
PDL14
7
6
PDL7
PDL6
Bit position
Bit name
15 to 0
PDLn
(n = 15 to 0)
In addition to their functions as port pins, in the control mode, the port DL pins operate as a data bus for when the
memory is externally expanded.
(1) Operation in control mode
Port
Port DL
PDL15 to
D15 to D0
PDL0
(2) I/O mode/control mode setting
The port DL I/O mode setting is performed by the port DL mode register (PMDL), and the control mode
setting is performed by the port DL mode control register (PMCDL).
(a) Port DL mode register (PMDL)
The port DL mode register (PMDL) can be read/written in 16-bit units.
If the higher 8 bits of PMDL are used as port DL mode register H (PMDLH), and the lower 8 bits as port
DL mode register L (PMDLL), these two 8-bit port mode registers can be read/written in 8-bit or 1-bit
units.
15
14
PMDL
PMDL15 PMDL14 PMDL13 PMDL12 PMDL11 PMDL10
7
6
PMDL7
PMDL6
Bit position
Bit name
15 to 0
PMDLn
(n = 15 to 0)
488
CHAPTER 14 PORT FUNCTIONS
13
12
11
PDL13
PDL12
PDL11
5
4
3
PDL5
PDL4
PDL3
Port DL
I/O port
Alternate Function Pin Name
13
12
11
5
4
3
PMDL5
PMDL4
PMDL3
Port Mode
Specifies input/output mode for PDLn pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
User's Manual U14359EJ4V0UM
10
9
8
PDL10
PDL9
PDL8
2
1
0
PDL2
PDL1
PDL0
Function
Remark
Data bus when memory expanded
10
9
8
PMDL9
PMDL8
2
1
0
PMDL2
PMDL1
PMDL0
Function
Address
After reset
FFFFF005H Undefined
Address
FFFFF004H
Block Type
O
Address
After reset
FFFFF025H
FFFFH
Address
FFFFF024H
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