Bus Hold Function; Function Outline - NEC V850E/MA1 User Manual

4.8 Bus Hold Function

4.8.1 Function outline

If the PCM2 and PCM3 pins are specified in the control mode, the HLDAK and HLDRQ functions become valid.
If it is determined that the HLDRQ pin has become active (low level) as a bus mastership request from another bus
master, the external address/data bus and each strobe pin are shifted to high impedance and then released (bus hold
state). If the HLDRQ pin becomes inactive (high level) and the bus mastership request is canceled, driving of these
pins begins again.
During the bus hold period, the internal operations of the V850E/MA1 continue until the external memory is
accessed.
The bus hold state can be known by the HLDAK pin becoming active (low level). The period from when the
HLDRQ pin becomes active (low level) to when the HLDAK pin becomes active (low level) is at least 2 clocks.
In a multiprocessor configuration, etc., a system with multiple bus masters can be configured.
State
CPU bus lock
Read modify write access of bit
manipulation instruction
Cautions 1. When an external bus master accesses EDO DRAM during a bus hold state, make sure that
the external bus master secures the RAS precharge time.
2. When an external bus master accesses SDRAM during a bus hold state, make sure that the
external bus master executes the all bank precharge command.
The CPU always executes the all bank precharge command to release a bus hold state. In a
bus hold state, do not allow an external bus master to change the SDRAM command
register value.
3. The HLDRQ function is invalid during a reset period. The HLDAK pin becomes active either
immediately after or after the insertion of a 1-clock address cycle from when the RESET pin
is set to inactive following the simultaneous activation of the RESET and HLDRQ pins.
When a bus master other than the V850E/MA1 is externally connected, use the RESET
signal for bus arbitration at power-on.
CHAPTER 4 BUS CONTROL FUNCTION
Data Bus Access Type
Width
16 bits Word access for even address
Word access for odd address
Halfword access for odd
address
8 bits Word access
Halfword access
−
User's Manual U14359EJ4V0UM
Timing at Which Bus Hold Request Cannot
Between first and second accesses
Between first and second accesses
Between second and third accesses
Between first and second accesses
Between first and second accesses
Between second and third accesses
Between third and forth accesses
Between first and second accesses
−
Between read access and write access
Be Acknowledged
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