Timer Status Register (Tsr) - Hitachi H8/3035 Series Hardware Manual

Bit 2 Bit 1 Bit 0
IOA2 IOA1 IOA0
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Notes: 1. After a reset, the output is 0 until the first compare match.
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
instead.

8.2.12 Timer Status Register (TSR)

TSR is an 8-bit register. The ITU has five TSRs, one in each channel.
Channel Abbreviation
0 TSR0
1 TSR1
2 TSR2
3 TSR3
4 TSR4
Function
GRA is an No output at compare match
output register
0 output at GRA compare match
1 output at GRA compare match
Output toggles at GRA compare match
(1 output in channel 2)
GRA is an input GRA captures rising edge of input
capture register
GRA captures falling edge of input
GRA captures both edges of input
Function
Indicates input capture, compare match, and overflow status
(Initial value)
*1
*1
*1, *2
191