Schematic Review Checklist; Processor Checklist (All Signals) - Intel Pentium 4 Design Manual

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15

Schematic Review Checklist

15.1

Processor Checklist (All Signals)

All signals of the processor are provided in this section.
Checklist Items
A[35:3]#
A20M#
ADS#
ADSTB[1:0]
AP[1:0]#
BCLK[1:0]
BINIT#
BNR#
BPRI#
® ®
Intel Pentium 4 Processor / Intel
Recommendations
• Connect A[31:3]# to MCH. Leave
A[35:32]# as No Connect.
• Connect to ICH2. No pull-up required.
• Connect to MCH
• Connect to MCH
• Leave as No Connect
• Connect to CK00 clock. Refer to clock
routing guidelines in the latest
revision of the design guide.
• Connect 33 Ω series resistor on each
clock signal.
• Connect a "shunt source termination
(Rt)" resistor to GND for each signal
on processor side of the series
resistor. The Rt value should be
49.9 Ω ±1% for 50 Ω MB impedance.
• Leave as No Connect.
• Connect to MCH
• Connect to MCH
®
850 Chipset Family Platform Design Guide
Schematic Review Checklist
Reason/Impact/Documentation
• Chipset does not support extended
addressing over 4 GB, leave A[35:32]#
unconnected.
• AGTL+ source synch I/O signal
• Asynch GTL+ Input Signal
• Refer to Section 5.4.1.2.
• AGTL+ common clock I/O signal
• AGTL+ source synch I/O signal
• Chipset does not support parity
protection on the address bus.
• AGTL+ common clock I/O signal
• Rt resistors should be selected to
match the characteristic impedance of
the board.
• System bus clock signal
• Refer to Section 4.1of this document.
• Chipset does not support this signal.
• AGTL+ common clock I/O signal
• AGTL+ common clock I/O signal
• AGTL+ common clock input signal
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