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Table 98.
CK410 Schematic Checklist
Signal Name
Note:
See CK410 Clock Synthesizer/Driver Specification for more details
PCIF_0/ITP_EN
PCIF_1,
PCIF_2
SRC[6:1]/
SRC[6:1]#
DOT96/DOT96#
PCI[5:0]
CPU[1:0]/
CPU[1:0]#
CPU_2/SRC_7,
CPU_2#/SRC_7#
FS_A
FS_B/
TEST_MODE
FS_C/TEST_SEL
REF
IREF
XTAL_IN/
XTAL_OUT
VTT_PWRGD#/
PD
VDD_PCI[1:0],
VDD_CPU,
VDD_SRC[3:1],
VDD_REF,
VDD_48,
VDD_A
VSS_48,
VSS_SRC,
VSS_CPU,
VSS_PCI[1:0],
VSS_REF
VSS_A
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
282
®
Intel
EP80579 Integrated Processor Product Line—Layout Checklist
Trace Geometry and
Impedance
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Zo = 50
Ω
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Length Requirements
• Connect to a 14.318-MHz
• Connect to Platform
• VTT_PWRGD# is a 3.3V
CK410 Power Pins
• Connect to VCC3
• See
CK410 Ground Pins
• Connect to GND
• See
Order Number: 320068-005US
Comments
crystal, placed within 500
mils of CK410 device.
VRMPWRGD signal after a
2ms delay.
LVTTL input. It acts as a
level sensitive strobe to
latch the FS pins and
other multiplexed inputs.
After VTT_PWRGD#
assertiion, it becomes a
real time input for
asserting power down.
Section 8.3.4, "CK410
Power Plane Filtering"
for
Power Filtering and
Decoupling guidelines.
Section 8.3.4, "CK410
Power Plane Filtering"
for
Ground Filtering and
Decoupling guidelines.
May 2010
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