Tpc Output Control Register (Tpcr) - Hitachi H8/3035 Series Hardware Manual

9.2.9 TPC Output Control Register (TPCR)

TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on
a group-by-group basis.
Bit 7
G3CMS1
Initial value 1
Read/Write R/W
Group 3 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 3
(TP to TP )
15 12
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match event that triggers TPC output group 3 (TP
Bit 7 Bit 6
G3CMS1 G3CMS0
0 0
1
1 0
1
6 5
G3CMS0 G2CMS1 G2CMS0
1 1
R/W R/W R/W
Group 2 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 2
(TP to TP )
11 8
Description
TPC output group 3 (TP
ITU channel 0
TPC output group 3 (TP
ITU channel 1
TPC output group 3 (TP
ITU channel 2
TPC output group 3 (TP
compare match in ITU channel 3
4 3 2
G1CMS1 G1CMS0
1 1 1
R/W R/W
Group 1 compare
match select 1 and 0
These bits select
the compare match
Group 0 compare
event that triggers
match select 1 and 0
TPC output group 1
These bits select
(TP to TP )
7 4
the compare match
event that triggers
TPC output group 0
(TP to TP )
to TP
15
to TP ) is triggered by compare match in
15 12
to TP ) is triggered by compare match in
15 12
to TP ) is triggered by compare match in
15 12
to TP ) is triggered by
15 12
1 0
G0CMS1 G0CMS0
1 1
R/W R/W
3 0
).
12
(Initial value)
265