Hitachi H8/3035 Series Hardware Manual page 196

Bit 3—Master Enable TIOCB
Bit 3
EB3 Description
0 TIOCB output is disabled regardless of TIOR3 and TFCR settings (TIOCB
3
operates as a generic input/output pin).
If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.
1 TIOCB is enabled for output according to TIOR3 and TFCR settings
3
Bit 2—Master Enable TIOCB
Bit 2
EB4 Description
0 TIOCB output is disabled regardless of TIOR4 and TFCR settings (TIOCB
4
operates as a generic input/output pin).
If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1.
1 TIOCB is enabled for output according to TIOR4 and TFCR settings
4
Bit 1—Master Enable TIOCA
Bit 1
EA4 Description
0 TIOCA output is disabled regardless of TIOR4, TMDR, and TFCR settings (TIOCA
4
operates as a generic input/output pin).
If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1.
1 TIOCA is enabled for output according to TIOR4, TMDR, and
4
TFCR settings
Bit 0—Master Enable TIOCA
Bit 0
EA3 Description
0 TIOCA output is disabled regardless of TIOR3, TMDR, and TFCR settings (TIOCA
3
operates as a generic input/output pin).
If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1.
1 TIOCA is enabled for output according to TIOR3, TMDR, and
3
TFCR settings
182
(EB3): Enables or disables ITU output at pin TIOCB
3
(EB4): Enables or disables ITU output at pin TIOCB
4
(EA4): Enables or disables ITU output at pin TIOCA
4
(EA3): Enables or disables ITU output at pin TIOCA
3
.
3
3
(Initial value)
.
4
4
(Initial value)
.
4
4
(Initial value)
.
3
3
(Initial value)