Table 5-3 Interrupt Sources, Vector Addresses, and Priority (cont)
Interrupt Source
IMIA3 (compare match/
input capture A3)
IMIB3 (compare match/
input capture B3)
OVI3 (overflow 3)
Reserved
IMIA4 (compare match/
input capture A4)
IMIB4 (compare match/
input capture B4)
OVI4 (overflow 4)
Reserved
ERI (receive error)
RXI (receive data full)
TXI (transmit data
empty)
TEI (transmit end)
Reserved
ADI (A/D end)
Note: * Lower 16 bits of the address.
84
Vector
Origin
Number Advanced Mode
ITU channel 3
36
37
38
—
39
ITU channel 4
40
41
42
—
43
—
44
45
46
47
48
49
50
51
SCI
52
53
54
55
—
56
57
58
59
A/D
60
Vector Address*
H'0090 to H'0093
H'0094 to H'0097
H'0098 to H'009B
H'009C to H'009F
H'00A0 to H'00A3
H'00A4 to H'00A7
H'00A8 to H'00AB
H'00AC to H'00AF
H'00B0 to H'00B3
H'00B4 to H'00B7
H'00B8 to H'00BB
H'00BC to H'00BF
H'00C0 to H'00C3
H'00C4 to H'00C7
H'00C8 to H'00CB
H'00CC to H'00CF
H'00D0 to H'00D3
H'00D4 to H'00D7
H'00D8 to H'00DB
H'00DC to H'00DF
H'00E0 to H'00E3
H'00E4 to H'00E7
H'00E8 to H'00EB
H'00EC to H'00EF
H'00F0 to H'00F3
IPR
Priority
IPRB7
IPRB6
—
IPRB3
IPRB2
IPRB1 Low