Hitachi H8/3035 Series Hardware Manual page 265

Table 8-11 (d) ITU Operating Modes (Channel 3)
TSNC
Synchro-
Operating Mode nization MDF
Synchronous preset SYNC3 = 1 —
PWM mode —
o
Output compare A o —
Output compare B —
o
Input capture A —
o
Input capture B —
o
Counter By compare —
o
clearing match/input
capture A
By compare —
o
match/input
capture B
Syn- SYNC3 = 1 —
chronous
clear
Complementary o *3 —
PWM mode
Reset-synchronized —
o
PWM mode
Buffering —
o
(BRA)
Buffering —
o
(BRB)
Legend: o Setting available (valid). — Setting does not affect this mode.
Notes: 1. Master enable bit settings are valid only during waveform output.
2. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
3. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.
4. The counter cannot be cleared by input capture A when reset-synchronized PWM mode is selected.
5. In complementary PWM mode, select the same clock source for channels 3 and 4.
6. Use the input capture A function in channel 1.
TMDR TFCR
Comple- Reset-
mentary Synchro-
FDIR PWM PWM nized PWM Buffering
— *3
o o o
— PWM3 = 1 CMD1 = 0 CMD1 = 0
— PWM3 = 0 CMD1 = 0 CMD1 = 0
— CMD1 = 0 CMD1 = 0
o
— PWM3 = 0 CMD1 = 0 CMD1 = 0
— PWM3 = 0 CMD1 = 0 CMD1 = 0
— Illegal setting: o *4
o
CMD1 = 1
CMD0 = 0
— CMD1 = 0 CMD1 = 0
o
— Illegal setting: o
o
CMD1 = 1
CMD0 = 0
— — CMD1 = 1 CMD1 = 1
CMD0 = 0 CMD0 = 0
— — CMD1 = 1 CMD1 = 1
CMD0 = 1 CMD0 = 1
—
o o o
—
o o o
Register Settings
TOCR TOER
Output
Level Master
XTGD Select Enable IOA
— — *1
o o o
— — —
o o
o — — o IOA2 = 0
Other bits
unrestricted
— —
o o o
— — EA3 ignored IOA2 = 1
o
Other bits Other bits
unrestricted unrestricted
— — EA3 ignored o
o
Other bits
unrestricted
— — *1
o o o
— —
o o *1 o
— — *1
o o o
o o *6 o o —
*6 —
o o o o
BFA3 = 1 — — *1
o o
Other bits
unrestricted
BFB3 = 1 — —
o *1 o
Other bits
unrestricted
TIOR3 TCR3
Clear Clock
IOB Select Select
o o o
*2
o o o
o o o
IOB2 = 0
o o
Other bits
unrestricted
o o o
IOA2 = 1
o o
Other bits
unrestricted
CCLR1 = 0 o
o
CCLR0 = 1
CCLR1 = 1 o
o
CCLR0 = 0
CCLR1 = 1 o
o
CCLR0 = 1
— CCLR1 = 0 o *5
CCLR0 = 0
— CCLR1 = 0 o
CCLR0 = 1
o o o
o o o
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