Hitachi H8/3035 Series Hardware Manual page 356

Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In
asynchronous mode the SCI operates on a base clock with 16 times the bit rate frequency. In
receiving, the SCI synchronizes internally with the fall of the start bit, which it samples on the
base clock. Receive data is latched at the rising edge of the eighth base clock pulse. See figure
11-21.
0
Internal
base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 11-21 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
1
M = | (0.5 – ) – (L – 0.5) F –
2N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
When D = 0.5, F = 0:
= [0.5 – 1/(2 × 16)] × 100%
M
= 46.875%
This is a theoretical value. A reasonable margin to allow in system design is 20% to 30%.
342
16 clocks
8 clocks
7
Start bit
| D – 0.5 |
(1 + F) |
N
(2)
15 0 7
D
0
×
100%
15 0
D
1