ADDRD H/L—A/D Data Register D H/L H'E6, H'E7
Bit
15
AD9
AD8
Initial value
0
Read/Write
R
ADCR—A/D Control Register
Bit
7
TRGE
Initial value
0
Read/Write
R/W
Trigger enable
0 A/D conversion cannot be externally triggered
1 A/D conversion starts at the fall of the external trigger signal (
496
14
13
12
11
10
AD7
AD6
AD5
AD4
AD3
0
0
0
0
0
R
R
R
R
R
R
ADDRDH
A/D conversion data
10-bit data giving an
A/D conversion result
H'E9
A/D
6
5
—
—
1
1
—
—
A/D
9
8
7
6
5
4
AD2
AD1
AD0
—
—
0
0
0
0
0
0
R
R
R
R
R
ADDRDL
4
3
2
—
—
—
1
1
1
—
—
—
3
2
1
0
—
—
—
—
0
0
0
0
R
R
R
R
1
0
—
—
1
1
—
—
ADTRG
)