16.2 Register Configuration
The system control register (SYSCR) controls the power-down state. Table 16-2 summarizes this
register.
Table 16-2 Control Register
Address* Name
H'FFF2
System control register
Note: * Lower 16 bits of the address.
16.2.1 System Control Register (SYSCR)
Bit
7
SSBY
Initial value
0
Read/Write
R/W
Software standby
Enables transition to
software standby mode
SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0)
control the power-down state. For information on the other SYSCR bits, see section 3.3, System
Control Register.
384
Abbreviation
SYSCR
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby timer select 2 to 0
These bits select the
waiting time at exit from
software standby mode
R/W
Initial Value
R/W
H'0B
3
2
1
UE
NMIEG
—
1
0
1
R/W
R/W
—
Reserved bit
NMI edge select
User bit enable
0
RAME
1
R/W
RAM enable