Table 17-6 Timing of On-Chip Supporting Modules (cont)
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 18 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol Min
SCI
Transmit data
tTXD
delay time
Receive data
tRXS
setup time
(synchronous)
Receive data
tRXH
hold time
(synchronous
clock input)
Receive data
tRXH
hold time
(synchronous
clock output)
Ports
Output data
tPWD
and
delay time
TPC
Input data setup
tPRS
time
(synchronous)
Input data hold
tPRH
time
(synchronous)
408
Condition A
Condition B
8 MHz
10 MHz
Max
Min
Max
—
100
—
100
100
—
100
—
100
—
100
—
0
—
0
—
—
100
—
100
50
—
50
—
50
—
50
—
– Preliminary –
Condition C
18 MHz
Test
Min
Max
Unit
Conditions
—
100
ns
Figure 17-
15
100
—
100
—
0
—
—
100
ns
Figure 17-
11
50
—
50
—