17.2.2 AC Characteristics
Bus timing parameters are listed in table 17-4. Control signal timing parameters are listed in
table 17-5. Timing parameters of the on-chip supporting modules are listed in table 17-6.
Table 17-4 Bus Timing – Preliminary –
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
Item
Symbol Min
Clock cycle time
tcyc
Clock low pulse width tCL
Clock high pulse width tCH
Clock rise time
tCR
Clock fall time
tCF
Address delay time
tAD
Address hold time
tAH
Address strobe delay
tASD
time
Write strobe delay
tWSD
time
Strobe delay time
tSD
Write data strobe
tWSW1* 85
pulse width 1
Write data strobe
tWSW2* 150
pulse width 2
Address setup time 1
tAS1
Address setup time 2
tAS2
Read data setup time
tRDS
Read data hold time
tRDH
VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
VSS = AVSS = 0 V, ø = 2 MHz to 18 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A
Condition B
8 MHz
10 MHz
Max
Min
125
500
100
40
—
30
40
—
30
—
20
—
—
20
—
—
60
—
25
—
20
—
60
—
—
60
—
—
60
—
—
60
—
110
20
—
15
80
—
65
50
—
35
0
—
0
Condition C
18 MHz
Max
Min
Max
500
55.5
500
—
17
—
—
17
—
15
—
10
15
—
10
50
—
25
—
10
—
40
—
25
50
—
25
50
—
25
—
32
—
—
62
—
—
10
—
—
38
—
—
15
—
—
0
—
Test
Unit
Conditions
ns
Figure 17-4,
Figure 17-5
403