Table 17-4 Bus Timing (cont)
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
Item
Symbol Min
Write data delay
tWDD
time
Write data setup
tWDS1
time 1
Write data setup
tWDS2
time 2
Write data hold time tWDH
Read data access
tACC1*
time 1
Read data access
tACC2*
time 2
Read data access
tACC3*
time 3
Read data access
tACC4*
time 4
Precharge time
tPCH*
Wait setup time
tWTS
Wait hold time
tWTH
(Notes on next page)
404
– Preliminary –
VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
VSS = AVSS = 0 V, ø = 2 MHz to 18 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A
Condition B
8 MHz
10 MHz
Max
Min
—
75
—
60
—
40
5
—
–10
25
—
20
—
120
—
—
240
—
—
70
—
—
180
—
85
—
60
40
—
40
10
—
10
Condition C
18 MHz
Max
Min
Max
75
—
55
—
10
—
—
–10
—
—
20
—
100
—
50
200
—
105
50
—
20
150
—
80
—
40
—
—
25
—
—
5
—
Test
Unit
Conditions
ns
Figure 17-4,
Figure 17-5
ns
Figure 17-6