Tsr0-Timer Status Register 0 H'67 Itu0 - Hitachi H8/3035 Series Hardware Manual

TSR0—Timer Status Register 0 H'67
Bit 7
—
Initial value 1
Read/Write —
Input capture/compare match flag B
Overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT overflowed from H'FFFF to H'0000
Note: Only 0 can be written, to clear the flag.
*
ITU0
6 5
— —
1 1
— —
Input capture/compare match flag A
0 [Clearing condition]
Read IMFA when IMFA = 1, then write 0 in IMFA
1 [Setting conditions]
TCNT = GRA when GRA functions as a compare
match register.
TCNT value is transferred to GRA by an input capture
signal, when GRA functions as an input capture register.
0 [Clearing condition]
Read IMFB when IMFB = 1, then write 0 in IMFB
1 [Setting conditions]
TCNT = GRB when GRB functions as a compare
match register.
TCNT value is transferred to GRB by an input capture
signal, when GRB functions as an input capture register.
4 3 2
— — OVF
1 1 0
— — R/(W)
*
1 0
IMFB IMFA
0 0
R/(W) R/(W)
* *
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