Hitachi H8/3035 Series Hardware Manual page 202

Bits 6 and 5 —Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared.
Bit 6 Bit 5
CCLR1 CCLR0
0 0
1
1 0
1
Notes: 1. TCNT is cleared by compare match when the general register functions as a compare
match register, and by input capture when the general register functions as an input
capture register.
2. Selected in the timer synchro register (TSNC).
Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges
when an external clock source is used.
Bit 4 Bit 3
CKEG1 CKEG0
0 0
1
1 —
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored.
Phase counting takes precedence.
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock
source.
Bit 2 Bit 1
TPSC2 TPSC1
0 0
1
1 0
1
188
Description
TCNT is not cleared
TCNT is cleared by GRA compare match or input capture
TCNT is cleared by GRB compare match or input capture
Synchronous clear: TCNT is cleared in synchronization with other
synchronized timers
*2
Description
Count rising edges
Count falling edges
Count both edges
Bit 0
TPSC0 Function
0 Internal clock: ø
1 Internal clock: ø/2
0 Internal clock: ø/4
1 Internal clock: ø/8
0 External clock A: TCLKA input
1 External clock B: TCLKB input
0 External clock C: TCLKC input
1 External clock D: TCLKD input
(Initial value)
*1
*1
(Initial value)
(Initial value)