Hitachi H8/3035 Series Hardware Manual page 276

Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are
triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3)
is H'FFA4 and the address of the lower 4 bits (group 2) is H'FFA6. Bits 3 to 0 of address H'FFA4
and bits 7 to 4 of address H'FFA6 are reserved bits that cannot be modified and always read 1.
Address H'FFA4
Bit 7
NDR15
Initial value 0
Read/Write R/W
Address H'FFA6
Bit 7
—
Initial value 1
Read/Write —
262
6 5 4
NDR14 NDR13 NDR12
0 0 0
R/W R/W R/W
Next data 15 to 12
These bits store the next output
data for TPC output group 3
6 5 4
— — —
1 1 1
— — —
Reserved bits
3 2
— —
1 1
— —
Reserved bits
3 2 1
NDR11 NDR10 NDR9
0 0
0
R/W R/W R/W
Next data 11 to 8
These bits store the next output
data for TPC output group 2
1 0
— —
1 1
— —
0
NDR8
0
R/W