Hitachi H8/3035 Series Hardware Manual page 544

ø
RES
Internal
reset signal
Address bus
(mode 1)
AS (mode 1)
RD (read access)
(mode 1)
WR (write access)
(mode 1)
Data bus
(write access)
(mode 1)
I/O port
(modes 1 to 3)
Figure D-2 Reset during Memory Access (Reset during T
Reset in T State: Figure D-3 is a timing diagram for the case in which
3
the T state of an external memory access cycle. As soon as
3
initialized to the input state.
impedance state. The address bus outputs are held during the T
when a reset occurs in the T
530
Access to external address
T
1
$6 5' :5
, , and go high, and the data bus goes to the high-
state of an access cycle to a two-state-access area.
2
T T
2 3
H'000000
High impedance
High impedance
State)
2
5(6
goes low during
5(6
goes low, all ports are
state.The same timing applies
3