Hitachi H8/3035 Series Hardware Manual page 5

5.2 Register Descriptions ...................................................................................................... 72
5.2.1 System Control Register (SYSCR)..................................................................... 72
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................ 74
5.2.3 IRQ Status Register (ISR) .................................................................................. 79
5.2.4 IRQ Enable Register (IER) ................................................................................ 80
5.2.5 IRQ Sense Control Register (ISCR) ................................................................... 80
5.3 Interrupt Sources............................................................................................................. 81
5.3.1 External Interrupts ............................................................................................. 81
5.3.2 Internal Interrupts .............................................................................................. 82
5.3.3 Interrupt Vector Table ....................................................................................... 83
5.4 Interrupt Operation.......................................................................................................... 85
5.4.1 Interrupt Handling Process................................................................................. 85
5.4.2 Interrupt Sequence ............................................................................................. 91
5.4.3 Interrupt Response Time.................................................................................... 92
5.5 Usage Notes.................................................................................................................... 92
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ...................... 92
5.5.2 Instructions that Inhibit Interrupts ...................................................................... 93
5.5.3 Interrupts during EEPMOV Instruction Execution ............................................. 94
5.5.4 Usage Notes....................................................................................................... 94
Section 6 Bus Controller ................................................................................97
6.1 Overview ........................................................................................................................ 97
6.1.1 Features ............................................................................................................. 97
6.1.2 Block Diagram................................................................................................... 98
6.1.3 Input/Output Pins............................................................................................... 98
6.1.4 Register Configuration....................................................................................... 99
6.2 Register Descriptions ...................................................................................................... 99
6.2.1 Access State Control Register (ASTCR) ............................................................ 99
6.2.2 Wait Control Register (WCR)............................................................................ 100
6.2.3 Wait State Controller Enable Register (WCER)................................................. 101
6.2.4 Address Control Register (ADRCR)................................................................... 102
6.3 Operation ........................................................................................................................ 104
6.3.1 Area Division..................................................................................................... 104
6.3.2 Bus Control Signal Timing ................................................................................ 106
6.3.3 Wait Modes ....................................................................................................... 108
6.3.4 Interconnections with Memory (Example) ......................................................... 114
6.4 Usage Notes.................................................................................................................... 116
6.4.1 Register Write Timing ....................................................................................... 116
6.4.2 Precautions on setting ASTCR and ABWCR* ................................................... 116
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