Realtek Ameba-D RTL872 D Series User Manual page 403


The Slave Enable Register (SER) can be written here to enable the target slave for selection. If a slave is enabled here, the transfer
begins as soon as one valid data entry is present in the transmit FIFO. If no slaves are enabled prior to writing to the Data Register
(DR), the transfer does not begin until a slave is enabled.
(3) Enable the SPI by writing 1 to the SSIENR register.
(4) Write data for transmission to the target slave into the transmit FIFO (write DR).
If no slaves were enabled in the SER register at this point, enable it now to begin the transfer.
(5) Poll the BUSY status to wait for completion of the transfer. The BUSY status cannot be polled immediately; for more information, see the
note on page 40.
If a transmit FIFO empty interrupt request is made, write the transmit FIFO (write DR). If a receive FIFO full interrupt request is made,
read the receive FIFO (read DR).
(6) The transfer is stopped by the shift control logic when the transmit FIFO is empty. If the transfer mode is receive only (TMOD = 2'b10),
the transfer is stopped by the shift control logic when the specified number of frames have been received. When the transfer is done, the
BUSY status is reset to 0.
(7) If the transfer mode is not transmit only (TMOD != 01), read the receive FIFO until it is empty.
(8) Disable the SPI by writing 0 to SSIENR.
19.2.3.2 Serial-Slave Mode
SPI slave enables serial communication with master peripheral devices. When the SPI is configured as a slave device, all serial transfers are
initiated and controlled by the serial bus master.
Ameba-D SPI slave can only operates in transmit and receive mode. That is, TMOD field in
want this device to respond with data, slave output can be disabled through SLV_OE bit in CTRLR0.
When the SPI serial slave is selected during configuration, it enables its txd data onto the serial bus. All data transfers to and from the serial
slave are regulated on the serial clock line (sclk_in), driven from the serial-master device. Data are propagated from the serial slave on one
edge of the serial clock line and sampled on the opposite edge.
When the SPI serial slave is not selected, it must not interfere with data transfers between the serial-master and other serial-slave devices.
When the serial slave is not selected, its txd output is buffered, resulting in a high impedance drive onto the serial master rxd line.
The serial clock that regulates the data transfer is generated by the serial-master device and input to the SPI slave on sclk_in. The slave remains
in an idle state until selected by the bus master. When not actively transmitting data, the slave must hold its txd line in a high impedance state
to avoid interference with serial transfers to other slave devices. The slave continues to transfer data to and from the master device as long as
it is selected.
19.2.3.2.1 Slave SPI Serial Transfers
If the SPI slave transmits data to the master, you must ensure that data exists in the transmit FIFO before a transfer is initiated by the serial-
master device. If the master initiates a transfer to the SPI slave when no data exists in the transmit FIFO, an error flag (TXE) is set in the SPI
status register, and the previously transmitted data frame is resent on txd. For continuous data transfers, you must ensure that the transmit
FIFO buffer does not become empty before all the data have been transmitted. The transmit FIFO threshold level register (TXFTLR) can be used
to early interrupt (ssi_txe_intr) the processor, indicating that the transmit FIFO buffer is nearly empty. When a DMA Controller is used for APB
accesses, the DMA transmit data level register (DMATDLR) can be used to early request (dma_tx_req) the DMA Controller, indicating that the
transmit FIFO is nearly empty. The FIFO can then be refilled with data to continue the serial transfer.
The receive FIFO buffer should be read each time the receive FIFO generates a FIFO full interrupt request to prevent an overflow. The receive
FIFO threshold level register (RXFTLR) can be used to give early indication that the receive FIFO is nearly full. When a DMA Controller is used for
APB accesses, the DMA receive data level register (DMARDLR) can be used to early request (dma_rx_req) the DMA controller, indicating that
the receive FIFO is nearly full.
A typical software flow for completing a continuous serial transfer from a serial master to the SPI slave is described as follows:
(1) If the SPI slave is enabled, disable it by writing 0 to the SSI Enable register (SSIENR).
(2) Set up the SPI control registers for the transfer. These registers can be set in any order.

Write CTRLR0 (for SPI transfers SCPH and SCPOL must be set identical to the master device).

Write TXFTLR and RXFTLR to set FIFO threshold levels.

Write the IMR register to set up interrupt masks.
(3) Enable the SPI slave by writing 1 to SSIENR.
User Manual All information provided in this document is subject to legal disclaimers.
403
Serial Peripheral Interface (SPI)
CTRLR0 register is invalid for SPI slave. If you do not
© REALTEK 2019. All rights reserved.