Realtek Ameba-D RTL872 D Series User Manual page 310


Size: 32 bits

Address offset: 0x001C

Read/write access: read
31 30
23 22
15 14
RSVD
7 6
IR_RX_STATE
RSVD
R
Bit Name
31:18 RSVD
17 IR_RX_FIFO_EMPTY
16 IR_RX_FIFO_FULL
15:14 RSVD
13:8 IR_RX_FIFO_OFFSET
7 IR_RX_STATE
6 RSVD
5 IR_RX_FIFO_ERROR_INT_STATUS
4 IR_RX_CNT_THR_INT_STATUS
3 IR_RX_FIFO_OF_INT_STATUS
2 IR_RX_CNT_OF_INT_STATUS
1 IR_RX_FIFO_LEVEL_INT_STATUS
0 IR_RX_FIFO_FULL_INT_STATUS
15.3.3.3 IR_RX_INT_CLR

Name: IR clock division register

Size: 32 bits

Address offset: 0x0020

Read/write access: write
31 30
User Manual
29 28
21 20
RSVD
13 12
5 4
IR_RX_FIFO_ERROR IR_RX_CNT_THR
_INT_STATUS _INT_STATUS
R R
Access
N/A
R
R
N/A
R
R
N/A
R
R
R
R
R
R
29
RSVD
All information provided in this document is subject to legal disclaimers.
27 26
RSVD
19 18
11 10
IR_RX_FIFO_OFFSET
R
3
IR_RX_FIFO_OF_I IR_RX_CNT_O
NT_STATUS F_INT_STATUS
R
Reset Description
0 Reserved

0x0 0: Not empty

1: Empty

0x0 0: Not full

1: Full
0 Reserved
0x0 Rx FIFO offset

0x0 0: Idle

1: Run
0 Reserved
0x0 Rx FIFO error read interrupt status
When Rx FIFO is empty, reading the Rx FIFO triggers this interrupt.

0: Interrupt is inactive

1: Interrupt is active
0x0 Rx count threshold interrupt status

0: Interrupt is inactive

1: Interrupt is active
0x0 Rx FIFO overflow interrupt status

0: Interrupt is inactive

1: Interrupt is active
0x0 Rx counter overflow interrupt status

0: Interrupt is inactive

1: Interrupt is active
0x0 Rx FIFO level interrupt status

0: Interrupt is inactive

1: Interrupt is active
0x0 Rx FIFO full interrupt status

0: Interrupt is inactive

1: Interrupt is active
... 11
310
Ameba-D User Manual
25
17
IR_RX_FIFO_EMPTY
R
9
2 1
IR_RX_FIFO_LEVEL_I
NT_STATUS
R R
10 9
© REALTEK 2019. All rights reserved.
24
16
IR_RX_FIFO_FULL
R
8
0
IR_RX_FIFO_FULL_I
NT_STATUS
R
8
IR_RX_FIFO_CLR
WC