Realtek Ameba-D RTL872 D Series User Manual page 150


Destination scatter count field (DSRx.DSC) – Specifies the number of contiguous destination transfers of CTLx.DST_TR_WIDTH between
successive scatter boundaries.

Destination scatter interval field (DSRx.DSI) – Specifies the destination address increment/decrement in multiples of CTLx.DST_TR_WIDTH
on a scatter boundary when scatter mode is enabled for the destination transfer.
Note: If DMAH_RETURN_ERR_RESP is set to True, the DMAC returns an ERROR response to an illegal register access, which includes accessing
registers that have been removed during DMAC configuration. If DMAH_RETURN_ERR_RESP is set to False, DMAC always returns an OK
response.
The CTLx.DINC field controls whether the address increments or decrements. When the CTLx.DINC field indicates a fixed address control, then
the address remains constant throughout the transfer and the DSRx register is ignored. This register does not exist if the configuration
parameter DMAH_CHx_DST_SCA_EN is set to False.
Bit Name
63:32 RSVD
b:20 DSC
(See description)
19:0 DSI
9.3.2.3 Interrupt Registers
The following sections describe the registers pertaining to interrupts, their status, and how to clear them. For each channel, there are five
types of interrupt sources:

IntBlock – Block Transfer Complete Interrupt
This interrupt is generated on DMA block transfer completion to the destination peripheral.

IntDstTran – Destination Transaction Complete Interrupt
This interrupt is generated after completion of the last AHB transfer of the requested single/burst transaction from the handshaking
interface on the destination side.
Note: If the destination for a channel is memory, then that channel will never generate the IntDstTran interrupt. Because of this, the
corresponding bit in this field will not be set.

IntErr – Error Interrupt
This interrupt is generated when an ERROR response is received from an AHB slave on the HRESP bus during a DMA transfer. In addition,
the DMA transfer is cancelled and the channel is disabled.

IntSrcTran – Source Transaction Complete Interrupt
This interrupt is generated after completion of the last AHB transfer of the requested single/burst transaction from the handshaking
interface on the source side.
Note: If the source or destination is memory, then IntSrcTran/IntDstTran interrupts should be ignored, as there is no concept of a "DMA
transaction level" for memory.

IntTfr – DMA Transfer Complete Interrupt
This interrupt is generated on DMA transfer completion to the destination peripheral.
There are several groups of interrupt-related registers:

RawBlock, RawDstTran, RawErr, RawSrcTran, RawTfr

StatusBlock, StatusDstTran, StatusErr, StatusSrcTran, StatusTfr

MaskBlock, MaskDstTran, MaskErr, MaskSrcTran, MaskTfr

ClearBlock, ClearDstTran, ClearErr, ClearSrcTran, ClearTfr

StatusInt
When a channel has been enabled to generate interrupts, the following is true:

Interrupt events are stored in the Raw Status registers.

The contents of the Raw Status registers are masked with the contents of the Mask registers.

The masked interrupts are stored in the Status registers.

The contents of the Status registers are used to drive the int_* port signals.

Writing to the appropriate bit in the Clear registers clears an interrupt in the Raw Status registers and the Status registers on the same
clock cycle.
User Manual
Access Reset Description
N/A 0x0 Reserved
R/W 0x0 Destination scatter count. Destination contiguous transfer count
between successive scatter boundaries.
Bit[31:b+1] do not exist and read 0.
R/W 0x0 Destination scatter interval.
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150
b = log (DMAH_CHx_MAX_BLK_SIZE + 1) + 19
2
Ameba-D User Manual
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