Realtek Ameba-D RTL872 D Series User Manual page 207

1 CNT_STOP
0 CNT_START
10.4.1.2 TIMx Control Register (TIMx_CR)

Name: TIMx control register (x = {0, 1, 2, 3})

Address offset: 0x04

Reset value: 0x00000000

Read/write access: read/write
31 30 29
Bit Name Access Reset
31:5 RSVD N/A -
4 ARPE R/W 0
3 RSVD N/A -
2 URS R/W 0
1 UDIS R/W 0
0 RSVD N/A -
10.4.1.3 TIMx Interrupt Enable Register (TIMx_DIER)

Name: TIMx interrupt enable register (x = {0, 1, 2, 3})

Address offset: 0x08

Reset value: 0x00000000

Read/write access: read/write
31 30 29
Bit Name
31:1 RSVD
0 UIE
User Manual
W 0 Counter stop

0: No action.

1: Disable the counter. Poll CNT_RUN to see the counter status. If CNT_RUN is 0, it
means that the counter has been disabled internally.
W 0 Counter start

0: No action.

1: Enable the counter. Poll CNT_RUN to see the counter status. If CNT_RUN is 1, it
means that the counter has been enabled internally.
... 7 6
RSVD
Description
Reserved
Auto-reload preload enable

0: The TIMx_ARR register isn't buffered.

1: The TIMx_ARR register isn't buffered.
Reserved
Update request source

0: Update events can be

Counter overflow

Setting the UG bit

1: Counter overflow generates an update event.
Update disable

0: UEV is enabled. Buffered registers are loaded with their preload values when UEV happens.

1: UEV is disabled. Shadow registers keep their value.
Reserved
28 11
RSVD
Access Reset Description
N/A - Reserved
R/W 0 Update interrupt enable

0: Update interrupt is disabled.

1: Update interrupt is enabled.
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5 4
ARPE
R/W
... 5 4
207
3 2 1
URS UDIS
RSVD
R/W R/W
3 2 1
© REALTEK 2019. All rights reserved.
General Timers
0
RSVD
0
UIE
R/W