Realtek Ameba-D RTL872 D Series User Manual page 410

31 30 29 28
Bit Name Access
31:6 RSVD N/A
5:0 TFT R/W
TFT value
0000_0000
0000_0001
0000_0010
0000_0011
...
1111_1100
1111_1101
1111_1110
1111_1111
19.3.2.7 RXFTLR

Name: Receive FIFO Threshold Level

Size: 6 bits

Address offset: 0x1C

Read/write access: read/write
This register controls the threshold value for the receive FIFO memory. It is impossible to write to this register when the SPI is enabled. The SPI
is enabled and disabled by writing to the SSIENR register.
31 30 29 28
Bit Name Access
31:6 RSVD N/A
5:0 RFT R/W
RFT value
0000_0000
0000_0001
0000_0010
0000_0011
...
User Manual
27 26 ... 11
RSVD
Reset Description
- Reserved
0x0 Transmit FIFO Threshold. Controls the level of entries (or below) at which the transmit FIFO controller
triggers an interrupt. The FIFO depth is 64; this register is sized to the number of address bits
needed to access the FIFO.
If you attempt to set this value greater than or equal to the depth of the FIFO, this field is not written
and retains its current value. When the number of transmit FIFO entries is less than or equal to this
value, the transmit FIFO empty interrupt is triggered. For field decode, refer to Table 19-3.
Table 19-3 TFT decode
Description
ssi_txe_intr is asserted when 0 data entry is present in transmit FIFO
ssi_txe_intr is asserted when 1 data entry is present in transmit FIFO
ssi_txe_intr is asserted when 2 data entries are present in transmit FIFO
ssi_txe_intr is asserted when 3 data entries are present in transmit FIFO
...
ssi_txe_intr is asserted when 252 data entries are present in transmit FIFO
ssi_txe_intr is asserted when 253 data entries are present in transmit FIFO
ssi_txe_intr is asserted when 254 data entries are present in transmit FIFO
ssi_txe_intr is asserted when 255 data entries are present in transmit FIFO
27 26 ... 11
RSVD
Reset Description
- Reserved
0x0 Receive FIFO Threshold. Controls the level of entries (or above) at which the receive FIFO
controller triggers an interrupt. The FIFO depth is configurable in the range 2-256. This register
is sized to the number of address bits needed to access the FIFO. If you attempt to set this
value greater than the depth of the FIFO, this field is not written and retains its current value.
When the number of receive FIFO entries is greater than or equal to this value + 1, the receive
FIFO full interrupt is triggered. For field decode, refer to Table 19-4.
Table 19-4 RFT decode
Description
ssi_rxf_intr is asserted when 1 or more data entry is present in receive FIFO
ssi_rxf_intr is asserted when 2 or more data entries are present in receive FIFO
ssi_rxf_intr is asserted when 3 or more data entries are present in receive FIFO
ssi_rxf_intr is asserted when 4 or more data entries are present in receive FIFO
...
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410
Ameba-D User Manual
6 5 4 3
TFT
R/W
6 5 4 3
RFT
R/W
© REALTEK 2019. All rights reserved.
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