Realtek Ameba-D RTL872 D Series User Manual page 462

26:25 RSVD N/A
24 RC_INT_EN R/W
23 PCE_INT_EN R/W
22 IDX_INT_EN R/W
21 RUF_INT_EN R/W
20 ROF_INT_EN R/W
19 PC_INT_EN R/W
18 DR_INT_EN R/W
17 CT_INT_EN R/W
16 OF_INT_EN R/W
15 UF_INT_EN R/W
14 IL_INT_EN R/W
13 CNT_SC R/W
12 DBN_EN R/W
11:5 RSVD N/A
4:3 PCHG_LV R/W
User Manual
-- Reserved
0 Rotation counter comparing interrupt enable control

1: Enable interrupt

0: Disable interrupt
This interrupt is asserted when the rotation counter is equal to the value of 'RCC'.
0 Position counter error interrupt enable control

1: Enable interrupt

0: Disable interrupt
This interrupt is asserted when the index pulse signal is detected but the position counter is
not equal to 0.
This bit is valid only when the index pulse detection is enabled (depending on IDX_EN).
0 Index pulse signal interrupt enable control

1: Enable interrupt

0: Disable interrupt
This interrupt is asserted when the index pulse signal presents.
This bit is valid only when the index pulse detection is enabled (depending on IDX_EN).
0 Rotation counter underflow interrupt enable control

1: Enable interrupt

0: Disable interrupt
This interrupt is asserted when the rotation counter underflow occurs (0  0xFFF).
0 Rotation counter overflow interrupt enable control

1: Enable interrupt

0: Disable interrupt
This interrupt is asserted when the rotation counter overflow occurs (0xFFF  0).
0 Position counter comparing interrupt enable control

1: Enable interrupt

0: Disable interrupt
This interrupt is asserted when the position counter is equal to the value of 'PCC'.
0 Movement direction changed interrupt enable control:

1: Enable interrupt

0: Disable interrupt
When the movement direction changes, this interrupt is asserted. Keep the direction at the
next state change if the Q-decoder is reset (perform QALL_RST or power on reset).
0 Position counter value changed interrupt enable control

1: Enable interrupt

0: Disable interrupt
When the position counter value changes and the difference (base on initial value or previous
interrupt triggered value) is over the level (depending on PCHG_LV), the position changed
interrupt is asserted.
Position counter value overflow (max position counter  0x0000) interrupt enable control
0

1: Enable interrupt

0: Disable interrupt
Position counter value underflow (0x0000  max position counter) interrupt enable control
0

1: Enable interrupt

0: Disable interrupt
0 Illegal state (phase A and phase B toggle simultaneously) detected interrupt enable control

1: Enable interrupt

0: Disable interrupt
0 This bit is used to configure the number of phase state changed for the position accumulation
counter to be increased/decreased by 1.

0: 1 phase.

1: 2 phases. Only phase A edges are counted.
0 Input signal (PHA, PHB & IDX) debouncing enable control

1: Enable debounce

0: Disable debounce
-- Reserved
0 Position changed interrupt trigger level
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Ameba-D User Manual
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