Realtek Ameba-D RTL872 D Series User Manual page 146


Address offset: for x = 0 to 7:

CFG0 – 0x040

CFG1 – 0x098

CFG2 – 0x0f0

CFG3 – 0x148

CFG4 – 0x1a0

CFG5 – 0x1f8

CFG6 – 0x250

CFG7 – 0x2a8

Read/write access: read/write
This register contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block
transfer.
Note: You need to program this register prior to enabling the channel.
Bit Name
63:47 RSVD
b:43 DEST_PER
(See notes)
b:39 SRC_PER
(See notes)
38 SS_UPD_EN
37 DS_UPD_EN
User Manual
Access Reset
N/A 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
All information provided in this document is subject to legal disclaimers.
Description
Reserved
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to
the destination of channel x if the CFGx.HS_SEL_DST field is 0; otherwise,
this field is ignored. The channel can then communicate with the
destination peripheral connected to that interface through the assigned
hardware handshaking interface.
Note 1: For correct DMA operation, only one peripheral (source or
destination) should be assigned to the same handshaking interface.
Note 2: This field does not exist if the configuration parameter
DMAH_NUM_HS_INT is set to 0.
Note 3:

b = 43 if DMAH_NUM_HS_INT is 1

b = ceil(log (DMAH_NUM_HS_INT)) + 42 if DMAH_NUM_HS_INT is
2
greater than 1
Bits 46:(b+1) do not exist and return 0 on a read.
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to
the source of channel x if the CFGx.HS_SEL_SRC field is 0; otherwise, this
field is ignored. The channel can then communicate with the source
peripheral connected to that interface through the assigned hardware
handshaking interface.
Note 1: For correct DMA operation, only one peripheral (source or
destination) should be assigned to the same handshaking interface.
Note 2: This field does not exist if the configuration parameter
DMAH_NUM_HS_INT is set to 0.
Note 3:

b = 39 if DMAH_NUM_HS_INT is 1

b = ceil(log (DMAH_NUM_HS_INT)) + 38 if DMAH_NUM_HS_INT is
2
greater than 1
Bits 42:(b+1) do not exist and return 0 on a read.
Source Status Update Enable. Source status information is fetched only
from the location pointed to by the SSTATARx register, stored in the SSTATx
register and written out to the SSTATx location of the LLI if SS_UPD_EN is
high.
Note: This enable is applicable only if DMAH_CHx_STAT_SRC is set to True.
This field does not exist if the configuration parameter
DMAH_CHx_STAT_SRC is set to False; in this case, the read-back value is
always 0.
Destination Status Update Enable. Destination status information is fetched
only from the location pointed to by the DSTATARx register, stored in the
DSTATx register and written out to the DSTATx location of the LLI if
DS_UPD_EN is high.
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Ameba-D User Manual
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