Realtek Ameba-D RTL872 D Series User Manual page 417

This register is only valid when SPI is configured with a set of DMA Controller interface signals.
31 30 29 28
Bit Name
31:2 RSVD
1 TDMAE
0 RDMAE
19.3.2.20 DMATDLR

Name: DMA Transmit Data Level Register

Size: 6 bits

Address offset: 0x50

Read/write access: read/write
This register is only valid when the SPI is configured with a set of DMA interface signals.
31 30 29 28 27
Bit Name
31:6 RSVD
5:0 DMATDL
DMATDL value
0000_0000
0000_0001
0000_0010
0000_0011
...
1111_1100
1111_1101
1111_1110
1111_1111
19.3.2.21 DMARDLR

Name: DMA Receive Data Level Register

Size: 6 bits

Address offset: 0x54

Read/write access: read/write
This register is only valid when SPI is configured with a set of DMA interface signals.
User Manual
27 26 25
Access Reset Description
N/A - Reserved
R/W 0 Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel.
0 – Transmit DMA disabled
1 – Transmit DMA enabled
R/W 0 Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel
0 – Receive DMA disabled
1 – Receive DMA enabled
26 25 ... 12
RSVD
Access Reset Description
N/A - Reserved
R/W 0x0 Transmit Data Level. This bit field controls the level at which a DMA request is made by
the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is
generated when the number of valid data entries in the transmit FIFO is equal to or below
this field value, and TDMAE = 1. Refer to Table 19-5 for the field decode.
Table 19-5 DMATDL decode value
Description
dma_tx_req is asserted when 0 data entry is present in transmit FIFO
dma_tx_req is asserted when 1 data entry is present in transmit FIFO
dma_tx_req is asserted when 2 data entries are present in transmit FIFO
dma_tx_req is asserted when 3 data entries are present in transmit FIFO
...
dma_tx_req is asserted when 252 data entries are present in transmit FIFO
dma_tx_req is asserted when 253 data entries are present in transmit FIFO
dma_tx_req is asserted when 254 data entries are present in transmit FIFO
dma_tx_req is asserted when 255 data entries are present in transmit FIFO
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... 8 7 6
RSVD
11 10 9 8
417
Serial Peripheral Interface (SPI)
5 4 3 2
7 6 5 4 3
DMATDL
R/W
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1 0
TDMAE RDMAE
R/W R/W
2 1 0