Realtek Ameba-D RTL872 D Series User Manual page 391

Bit Name
31:24 INT_ENABLE
23 RX_SNK_LR_SWAP
22 RX_SNK_BYTE_SWAP
21 TX_SRC_LR_SWAP
20 TX_SRC_BYTE_SWAP
19:18 RSVD
17 MODE_128FS
16 MODE_40MHZ
15:14 RSVD
13 CLEAR_RX_ERR_CNT
12 CLEAR_TX_ERR_CNT
11 RSVD
10:8 DEBUG_BUS_SEL
7:0 FRAME_SYNC_OFFSET
18.4.1.4 SP_CTRLR2

Name: SPORT control 2 register

Size: 32 bits

Address offset: 0x000C

Read/write access: read/write
31 30
5
RX_FIFO_DEPTH_HALF_SEL TX_FIFO_DEPTH_HALF_SEL
R/W
Bit Name
31:6 RSVD
5 RX_FIFO_DEPTH_HALF_SEL
4 TX_FIFO_DEPTH_HALF_SEL
3:0 RSVD
18.4.1.5 SP_RX_DR

Name: SPORT Rx data register

Size: 32 bits

Address offset: 0x0010

Read/write access: read
31 30 29 28
User Manual
FRAME_SYNC_OFFSET
Access Reset Description

R/W 8'h0

R/W 1'b0 1'b1: Swap L/R audio samples written to the sink memory

R/W 1'b0

R/W 1'b0

R/W 1'b0
N/A 6'h0 Reserved

R/W 1'b0


R/W 1'b0

N/A 2'b00 Reserved
R/W 1'b0 Write 1'b1 and then write 1'b0 to clear Rx error counter.
R/W 1'b0 Write 1'b1 and then write 1'b0 to clear Tx error counter.
N/A 1'b0 Reserved

R/W 3'h0



R/W 8'h81 To control the length of 'long_frame_sync' signal when it is ON.
It is set to 50% of the period of the sampling rate by default.
29
4 3
R/W
Access Reset Description
N/A 26'h0 Reserved
R/W 1'b0 1'b1: Rx FIFO depth will reduce to half. It can reduce the data path latency.
R/W 1'b0 1'b1: Tx FIFO depth will reduce to half. It can reduce the data path latency.
N/A 4'b0 Reserved
27 26 25 24
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R/W
0: For the interrupt of 'SP_READY_TO_TX'
1: For the interrupt of 'SP_READY_TO_RX'
1'b1: Swap H/L bytes written to the sink memory
1'b1: Swap L/R audio samples read from the source memory
1'b1: Swap H/L bytes read from the source memory
1'b1: Clock source is 128*fs
1'b0: Clock source is 256*fs
1'b1: Clock source is 40MHz
1'b0: Clock source is 128*fs or 256*fs
3'b000: debug_bus_a
3'b001: debug_bus_b
....
3'b111: debug_bus_h
... 8
RSVD
2
RSVD
... 7 6 5
SP_RX_DR
WR
391
Audio Codec Controller (ACC)
7 6
1 0
4 3 2 1
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