Realtek Ameba-D RTL872 D Series User Manual page 117

Direct Memory Access Controller (DMAC)
Fig 9-34 Source enters single transaction region when destination asserts dma_last[1]
Note: If an active level on dma_req[0] was triggered at time T6 or T7, a source burst transaction would have taken precedence over the source
single transaction. Upon completion of the source block, this burst transaction would have been early-terminated using an Early-Terminated
Burst Transaction.
When this transaction completes at time T8, the DMAC recognizes that enough data has been fetched from the source peripheral to complete
the block transfer to the destination. The DMAC asserts dma_finish[0] to the source peripheral at time T8; this has the same timing as
dma_ack[0]. The destination block transfer completes as previously described. No data loss occurs.
Case 2b – Data pre-fetching enabled but no data loss
In this case, the source does not enter the Single Transaction Region when the destination signals the last transaction. This case uses the
parameters listed in Table 9-10.
The destination block is made up of two burst transactions.
blk_size_bytes_dst = 2 * (4 * 4) = 32 bytes
As illustrated in Fig 9-35, the source requests a burst transaction at time T2 and completes the burst transaction at time T3. The destination
requests a burst transaction at time T1 and completes this burst request at time T4.
Fig 9-35 Case where source does not enter single transaction region when destination asserts dma_last[1]
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