Realtek Ameba-D RTL872 D Series User Manual page 143

0 INT_EN
CTLx.SRC_MSIZE/CTLx.DEST_MSIZE
000
001
010
011
100
101
110
111
CTLx.SRC_TR_WIDTH/ TLx.DST_TR_WIDTH
000
001
010
011
100
101
11x
CTLx.TT_FC Field
000
001
010
011
100
101
110
111
9.3.2.2.6 SSTATx

Name: Source Status Register for Channel x

Size: 64 bits (upper 32 bits are reserved)

Address offset: for x = 0 to 7:

SSTAT0 – 0x020

SSTAT1 – 0x078

SSTAT2 – 0x0d0

SSTAT3 – 0x128

SSTAT4 – 0x180

SSTAT5 – 0x1d8

SSTAT6 – 0x230

SSTAT7 – 0x288

Read/write access: read/write
User Manual
R/W 0x1
Table 9-15 CTLx.SRC_MSIZE and DEST_MSIZE decoding
Number of data items to be transferred (of width CTLx.SRC_TR_WIDTH or CTLx.DST_TR_WIDTH)
1
4
8
16
32
64
128
256
Table 9-16 CTLx.SRC_TR_WIDTH and CTLx.DST_TR_WIDTH decoding
Size (bits)
8
16
32
64
128
256
256
Table 9-17 CTLx.TT_FC field decoding
Transfer Type
Memory to Memory
Memory to Peripheral
Peripheral to Memory
Peripheral to Peripheral
Peripheral to Memory
Peripheral to Peripheral
Memory to Peripheral
Peripheral to Peripheral
All information provided in this document is subject to legal disclaimers.
Reset Value: Encoded value; refer to Table 9-16.
Dependencies: This field does not exist if DMAH_CHx_DTW is
hardcoded. In this case, the read-back value is always the
hardcoded destination transfer width, DMAH_CHx_DTW.
Interrupt Enable Bit. If set, then all interrupt-generating
sources are enabled. Functions as a global mask bit for all
interrupts for the channel; raw* interrupt registers still assert if
CTLx.INT_EN = 0.
Flow Controller
DMAC
DMAC
DMAC
DMAC
Peripheral
Source Peripheral
Peripheral
Destination Peripheral
143
Direct Memory Access Controller (DMAC)
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