Realtek Ameba-D RTL872 D Series User Manual page 409

This register is valid only when the SPI is configured as a master device. When the SPI is configured as a serial slave, writing to this location has
no effect; reading from this location returns 0. You cannot write to this register when SPI is busy.
31 30 29
15 14 13
Bit Name Access
31:1 RSVD N/A
0 SER R/W
19.3.2.5 BAUDR

Name: Baud Rate Select

Size: 16 bits

Address offset: 0x14

Read/Write access: read/write
This register is valid only when the SPI is configured as a master device. When the SPI is configured as a serial slave, writing to this location has
no effect; reading from this location returns 0. The register derives the frequency of the serial clock that regulates the data transfer. The 16-bit
field in this register defines the ssi_clk divider value. It is impossible to write to this register when the SPI is enabled. The SPI is enabled and
disabled by writing to the SSIENR register.
31 30 29
15 14 13
Bit Name Access
31:16 RSVD N/A
15:0 SCKDV R/W
19.3.2.6 TXFTLR

Name: Transmit FIFO Threshold Level

Size: 6 bits

Address offset: 0x18

Read/write access: read/write
This register controls the threshold value for the transmit FIFO memory. It is impossible to write to this register when the SPI is enabled. The
SPI is enabled and disabled by writing to the SSIENR register.
User Manual
28 27 26 25
12 11 10 9
Reset Description
- Reserved
0 Slave Select Enable Flag. When this bit is set (1), the corresponding slave select line from the
master is activated when a serial transfer begins. It should be noted that setting or clearing bits in
this register have no effect on the corresponding slave select outputs until a transfer is started.
Before beginning a transfer, you should enable the bit in this register that corresponds to the slave
device with which the master wants to communicate.
1 – Selected
0 – Not selected
28 27 26 25
12 11 10 9
Reset Description
- Reserved
0x0 SPI Clock Divider. The LSB for this field is always set to 0 and is unaffected by a write operation,
which ensures an even value is held in this register. If the value is 0, the serial output clock
(sclk_out) is disabled. The frequency of the sclk_out is derived from the following equation:
where SCKDV is any even value between 2 and 65534.
All information provided in this document is subject to legal disclaimers.
24 23 22 21
RSVD
8 7 6 5
RSVD
24 23 22 21
RSVD
8 7 6 5
SCKDV
R/W
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SCKDV
409
Serial Peripheral Interface (SPI)
20 19 18
4 3 2
20 19 18
4 3 2
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17 16
1 0
SER
R/W
17 16
1 0