Realtek Ameba-D RTL872 D Series User Manual page 392

Bit Name Access
31:0 SP_RX_DR R
18.4.1.6 SP_FIFO_SR

Name: SPORT FIFO status register

Size: 32 bits

Address offset: 0x0014

Read/write access: read
31 30
23 22
15 14
7 6
Bit Name
31:24 RX1_RCNT_BUS
23:16 RX0_RCNT_BUS
15:8 TX1_WCNT_BUS
7:0 TX0_WCNT_BUS
18.4.1.7 SP_ERROR_CNT_SR

Name: SPORT error counter register

Size: 32 bits

Address offset: 0x0018

Read/write access: read
31 30
23 22
15 14
7 6
Bit Name
31:16 RSVD
15:8 RX_ERR_CNT
7:0 TX_ERR_CNT
User Manual
Reset Description
32'h0 It's Rx data window between SW/GDMA and SPORT.
29 28
21 20
13 12
5 4
Access
R
R
R
R
29 28
21 20
13 12
5 4
Access Reset Description
N/A 16'h0 Reserved
R 8'h0 Rx error counter (MIC path)
Note: This counter should always be zero if everything works well.
R 8'h0 Tx error counter (SPK path)
Note: This counter should always be zero if everything works well.
All information provided in this document is subject to legal disclaimers.
27
RX1_RCNT_BUS
R
19
RX0_RCNT_BUS
R
11
TX1_WCNT_BUS
R
3
TX0_WCNT_BUS
R
Reset Description
8'h0 Rx1 FIFO read counter status (MIC path)
8'h0 Rx0 FIFO read counter status (MIC path)
8'h0 Tx1 FIFO write counter status (SPK path)
8'h0 Tx0 FIFO write counter status (SPK path)
27
RSVD
19
RSVD
11
RX_ERR_CNT
R
3
TX_ERR_CNT
R
392
Ameba-D User Manual
26 25
18 17
10 9
2 1
26 25
18 17
10 9
2 1
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16
8
0
24
16
8
0