Realtek Ameba-D RTL872 D Series User Manual page 149

CFGx.PROTCTL[1]
CFGx.PROTCTL[2] ->
CFGx.PROTCTL[3] ->
9.3.2.2.11 SGRx

Name: Source Gather Register for Channel x

Size: 64 bits (upper 32 bits are reserved)

Address offset: for x = 0 to 7:

SGR0 – 0x048

SGR1 – 0x0a0

SGR2 – 0x0f8

SGR3 – 0x150

SGR4 – 0x1a8

SGR5 – 0x200

SGR6 – 0x258

SGR7 – 0x2b0

Read/write access: read/write
The Source Gather register contains two fields:

Source gather count field (SGRx.SGC) – Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH between successive
gather intervals. This is defined as a gather boundary.

Source gather interval field (SGRx.SGI) – Specifies the source address increment/decrement in multiples of CTLx.SRC_TR_WIDTH on a
gather boundary when gather mode is enabled for the source transfer.
Note: If DMAH_RETURN_ERR_RESP is set to True, the DMAC returns an ERROR response to an illegal register access, which includes accessing
registers that have been removed during DMAC configuration. If DMAH_RETURN_ERR_RESP is set to False, DMAC always returns an OK
response.
The CTLx.SINC field controls whether the address increments or decrements. When the CTLx.SINC field indicates a fixed-address control, then
the address remains constant throughout the transfer and the SGRx register is ignored. This register does not exist if the configuration
parameter DMAH_CHx_SRC_GAT_EN is set to False.
Bit Name
63:32 RSVD
b:20 SGC
(See description)
19:0 SGI
9.3.2.2.12 DSRx

Name: Destination Scatter

Size: 64 bits (upper 32 bits are reserved)

Address offset: for x = 0 to 7:

DSR0 – 0x050

DSR1 – 0x0a8

DSR2 – 0x0100

DSR3 – 0x158

DSR4 – 0x1b0

DSR5 – 0x208

DSR6 – 0x260

DSR7 – 0x2b8

Read/write access: read/write
The Destination Scatter register contains two fields:
User Manual
Access Reset
N/A 0x0
R/W 0x0
R/W 0x0
Register for Channel x
All information provided in this document is subject to legal disclaimers.
HPROT[1]
HPROT[2]
HPROT[3]
Description
Reserved
Source gather count. Source contiguous transfer count between
successive gather boundaries.
b = log (DMAH_CHx_MAX_BLK_SIZE + 1) + 19
2
Bit[31:b+1] do not exist and read back as 0.
Source gather interval.
149
Direct Memory Access Controller (DMAC)
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