Realtek Ameba-D RTL872 D Series User Manual page 258

Note: It is not necessary to program any of the *CNT registers if the I
only to determine the SCL timing requirements for operation as an I
13.2.9.1 Minimum High and Low Counts
2 2
When the I C operates as an I

Minimum value that can be programmed in the *_LCNT registers is 8

Minimum value allowed for the *_HCNT registers is 6
The minimum value of 8 for the *_LCNT registers is due to the time required for the I
The minimum value of 6 for the *_HCNT register is due to the time required for the I
13.2.9.2 Programmable Duty Cycle
This section describes the minimum ic_clk frequencies that the I
values. It should be noted that these limits apply to the I
I 2 C does not break the Thd; dat maximum I
13.2.9.2.1 Calculating High and Low Counts
The calculations below show how to calculate SCL high and low counts for each speed mode in the I
Following conditions should be given:

Ic_clk frequency: fic_clk → IC_CLK_PERIOD=1/ fic_clk

Desired duty cycle: HIGH_TIME : LOW_TIME

SCL frequency: fSCL → SCL_PERIOD=1/ fSCL
While we want to get:

HIGH_COUNT & LOW_COUNT
We can derive the equations:
Then we can get:
Take Ameba-D I 2 C as an example:
 Ic_clk frequency: 10M → IC_CLK_PERIOD=100ns

Desired duty cycle:

100K: 40:47

400K: 6:13

SCL frequency:
 100K → SCL_PERIOD=10000ns
 400K → SCL_PERIOD=2500ns
Standard Speed Mode (100K):
40∗10000

IC_SS_SCL_HCNT =
( 40+47 ) ∗100
47∗10000

IC_SS_SCL_LCNT =
( 40+47 ) ∗100
User Manual
C master, in both transmit and receive transfers:
2 C in both master and slave modes. The limits for slave mode are required so that the
2 C protocol timing requirement.
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All information provided in this document is subject to legal disclaimers.
2
C is enabled to operate only as an I
2
C master.
2 C to drive SDA after a negative edge of SCL.
2
C to sample SDA during the high period of SCL.
2
C supports for each speed mode, and the associated high and low count
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= (2)
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258
Ameba-D User Manual
2
C slave, since these registers are used
2 C.
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