Realtek Ameba-D RTL872 D Series User Manual page 348

17.6.2.12 0x19
Address Bit Name
0x19 [15:0] ASRC_FTK_SDM_INI[15:0]
17.6.2.13 0x1A
Address Bit Name
0x1A [7:0] ASRC_FTK_SDM_INI[23:16]
[8] GEN_SRC_16K128_EN
[9] GEN_SRC_32K128_EN
[10] GEN_SRC_44P1K128_EN
[11] GEN_SRC_48K128_EN
[12] GEN_SRC_8K128_EN
[13] AD_ANA_CLK_SEL
[15:14] ASRC_FTK_LOOP_GAIN_SEL
17.6.2.14 0x1B
Address Bit Name
0x1B [0] AUDIO_IP_TCON_EN
[1] ASRC_FTK_LOOP_EN
[3:2] ASRC_256FS_SYS_SEL
[4] ASRC_EN
[6:5] SIDETONE_IN_SEL
User Manual

1'b0: Turn off clock

1'b1: Turn on clock
Access Reset Description
R/W 16'h0 Set initial value of tracked frequency
Access Reset
R/W 8'h0
R/W 1'b1
R/W 1'b1
R/W 1'b1
R/W 1'b1
R/W 1'b1
R/W 1'b0
R/W 2'b01
Access Reset Description
R/W 1'b1 Set audio ip tcon

1'b0: Disable and reset

1'b1: Enable
R/W 1'b0 Set loop filter enable

1'b0: Disable

1'b1: Enable
R/W 2'h0 Set clock of src_tcon

2'b00: 512*48K

2'b01: 1024*48K

2'b10: 2048*48K

2'b11: Reserved
R/W 1'b0 Set asynchronous sample rate conversion

1'b0: Disable

1'b1: Enable
R/W 2'h0 sidetone input selection

2'b00: From adc_l_lpf
All information provided in this document is subject to legal disclaimers.
348
Description
Set initial value of tracked frequency
Set 16k*128 clock

1'b0: Disable

1'b1: Enable
Set 32k*128 clock

1'b0: Disable

1'b1: Enable
Set 44.1k*128 clock

1'b0: Disable

1'b1: Enable
Set 48k*128 clock

1'b0: Disable

1'b1: Enable
Set 8k*128 clock

1'b0: Disable

1'b1: Enable
Set clk_ad_ana phase (reference clk_da_ana)

1'b0: Inphase

1'b1: Inverse phase
Set loop gain

2'b00: 2^-8

2'b01: 2^-14

2'b10: 2^-18

2'b11: 2^-20
Ameba-D User Manual
© REALTEK 2019. All rights reserved.