Realtek Ameba-D RTL872 D Series User Manual page 442

31:6 RSVD
5 FRM_START_INT
4 IO_TIMEOUT_INTEN
3 LCD_LIN_INTEN
2 LCDFRDINTEN
1 RSVD
0 DMAUNINTEN
20.3.2.2 LCDC_IRQ_STATUS

Name: LCDC interrupt status register

Size: 32 bits

Address offset: 0x0024

Read/write access: read/write
LCDC interrupt status after mask and interrupt clear register.
31 30
7 6
RSVD
Bit Name
31:6 RSVD
5 FRM_START_INTS
4 IO_TIMEOUT_INTS
3 LCD_LIN_INTS
2 LCDFRDINTS
1 RSVD
0 DMAUNINTS
User Manual
N/A 0 Reserved
R/W 0 DMA Frame start interrupt Enable. This bit can be set and cleared by software.

0: DMA Frame start interrupt disable

1: DMA Frame start interrupt enable
R/W 0 Write or read timeout interrupt Enable in MCU I/F I/O mode. This bit can be set and
cleared by software.

0: MCU I/O mode write/read timeout interrupt disable

1: MCU I/O mode write/read timeout interrupt enable
R/W 0 Line Interrupt Enable. This bit can be set and cleared by software.

0: Line interrupt disable

1: Line Interrupt enable
R/W 0 LCD refresh frame done interrupt enable
N/A 0 Reserved
R/W 0 DMA FIFO underflow interrupt enable
29
5 4
FRM_START_INTS IO_TIMEOUT_INTS
R/W1C R/W1C
Access Reset Description
N/A 0 Reserved
R/W1C 0 DMA frame start interrupt status. Write 1 to clear it.


R/W1C 0 Write or read timeout interrupt status in MCU I/F I/O mode. Write 1 to clear it.


R/W1C 0 Line Interrupt status. Write 1 to clear it.


Note: When this bit is set and DMA fetches the first pixel data of the specified line
number from frame buffer, the line interrupt happens. The line number depends
on LCDC_LINE_INT_POS register value.
R/W1C 0 LCD refresh frame done interrupt status. Write 1 to clear it.


Note: When this bit is set and DMA fetch the last pixel data from frame buffer, the
After LCD refresh frame done, interrupt happens.
N/A 0 Reserved
R/W1C 0 DMA FIFO underflow interrupt status. Write 1 to clear it.


All information provided in this document is subject to legal disclaimers.
...
RSVD
3
LCD_LIN_INTS
R/W1C
0: No DMA frame start interrupt generated
1: A DMA frame start interrupt is generated
0: No write/read timeout interrupt generated.
1: A write/read timeout interrupt is generated.
0: No Line interrupt generated
1: A Line interrupt is generated, when a programmed line is reached
0: No LCD refresh frame done interrupt generated
1: This interrupt generated, when sending LCD frame done.
0: No DMA FIFO underflow interrupt generated
1: Interrupt generated when DMA FIFO underflow happens
442
Ameba-D User Manual
10 9
2 1
LCDFRDINTS
RSVD
R/W1C
© REALTEK 2019. All rights reserved.
8
0
DMAUNINTS
R/W1C