Realtek Ameba-D RTL872 D Series User Manual page 175

Enabling the source or destination address to be contiguous between blocks is a function of the CTLx.LLP_SRC_EN, CFGx.RELOAD_SRC,
CTLx.LLP_DST_EN, and CTLx.RELOAD_DST registers (see Table 9-19).
Note: You cannot select both SARx and DARx updates to be contiguous. If you want this functionality, you should increase the size of the Block
Transfer (CTLx.BLOCK_TS), or if this is at the maximum value, use Row 10 of Table 9-19 and set up the LLI.SARx address of the block descriptor
to be equal to the end SARx address of the previous block. Similarly, set up the LLI.DARx address of the block descriptor to be equal to the end
DARx address of the previous block. For more information, refer to "Multi-Block Transfer with Linked List for Source and Linked List for
Destination (Row 10)"
9.4.3.4 Suspension of Transfers between Blocks
At the end of every block transfer, an end-of-block interrupt is asserted if:
(1) Interrupts are enabled, CTLx.INT_EN = 1, and
(2) The channel block interrupt is unmasked, MaskBlock[n] = 1, where n is the channel number.
Note: The block-complete interrupt is generated at the completion of the block transfer to the destination.
For rows 6, 8, and 10 of Table 9-19, the DMA transfer does not stall between block transfers. For example, at the end-of-block N, the DMAC
automatically proceeds to block N + 1.
For rows 2, 3, 4, 7, and 9 of Table 9-19 (SARx and/or DARx auto-reloaded between block transfers), the DMA transfer automatically stalls after
the end-of-block interrupt is asserted, if the end-of-block interrupt is enabled and unmasked.
The DMAC does not proceed to the next block transfer until a write to the ClearBlock[n] block interrupt clear register, done by software to
clear the channel block-complete interrupt, is detected by hardware.
For rows 2, 3, 4, 7, and 9 of Table 9-19 (SARx and/or DARx auto-reloaded between block transfers), the DMA transfer does not stall if either:

Interrupts are disabled, CTLx.INT_EN = 0, or

The channel block interrupt is masked, MaskBlock[n] = 0, where n is the channel number.
Channel suspension between blocks is used to ensure that the end-of-block ISR (interrupt service routine) of the next-to-last block is serviced
before the start of the final block commences. This ensures that the ISR has cleared the CFGx.RELOAD_SRC and/or CFGx.RELOAD_DST bits
before completion of the final block. The reload bits CFGx.RELOAD_SRC and/or CFGx.RELOAD_DST should be cleared in the end-of-block ISR for
the next-to-last block transfer.
9.4.3.5 Ending Multi-Block Transfers
All multi-block transfers must end as shown in either Row 1 or Row 5 of Table 9-19. At the end of every block transfer, the DMAC samples the
row number, and if the DMAC is in the Row 1 or Row 5 state, then the previous block transferred was the last block and the DMA transfer is
terminated.
Note: Row 1 and Row 5 are used for single-block transfers or terminating multi-block transfers. Transfers initiated in rows 2, 3 or 4 can only
end in row 1; similarly, transfers initiated in rows 6 through 10 can only end in row 5. Ending in the Row 5 state enables status fetch and write-
back for the last block. Ending in the Row 1 state disables status fetch and write-back for the last block.
For rows 2, 3, and 4 of Table 9-19, (LLPx.LOC = 0 and CFGx.RELOAD_SRC and/or CFGx.RELOAD_DST is set), multi-block DMA transfers continue
until both the CFGx.RELOAD_SRC and CFGx.RELOAD_DST registers are cleared by software. They should be programmed to 0 in the end-of-
block interrupt service routine that services the next-to-last block transfer; this puts the DMAC into the Row 1 state.
For rows 6, 8, and 10 of Table 9-19 (both CFGx.RELOAD_SRC and CFGx.RELOAD_DST cleared), the user must set up the last block descriptor in
memory so that both LLI.CTLx.LLP_SRC_EN and LLI.CTLx.LLP_DST_EN are 0.
The sampling of the LLPx.LOC bit takes place exclusively at the beginning of the transfer when the channel is enabled. This determines whether
writeback is enabled throughout the complete transfer, and changing the value of this bit in subsequent blocks on the same transfer does not
have any effect.
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Direct Memory Access Controller (DMAC)
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