Realtek Ameba-D RTL872 D Series User Manual page 174

No. Transfer Type LLP.LOC=0
1 Single-block or last Yes
transfer of multi-
block
2 Auto-reload multi- Yes
block transfer with
contiguous SAR
3 Auto-reload multi- Yes
block transfer with
contiguous DAR
4 Auto-reload multi- Yes
block transfer
5 Single-block or last No
transfer of multi-
block
6 Linked list multi- No
block transfer with
contiguous SAR
7 Linked list multi- No
block transfer with
auto-reload SAR
8 Linked list multi- No
block transfer with
contiguous DAR
9 Linked list multi- No
block transfer with
auto-reload DAR
10 Linked list multi- No
block transfer
Note:

Throughout this databook, there are descriptions about fetching the LLI.CTLx register from the location pointed to by the LLPx register.
This exact location is the LLI base address (stored in LLPx register) plus the fixed offset. For example, in Fig 9-47, the location of the
LLI.CTLx register is LLPx.LOC + 0xc.

Referring to Table 9-19, if the Write Back column entry is "Yes" and the configuration parameter DMAH_CHx_CTL_WB_EN = True, then
the CTLx[63:32] register is always written to system memory (to LLI.CTLx[63:32]) at the end of every block transfer. The source status is
fetched and written to system memory at the end of every block transfer if the Write Back column entry is "Yes,"
DMAH_CHx_CTL_WB_EN = True, DMAH_CHx_STAT_SRC = True, and CFGx.SS_UPD_EN is enabled. The destination status is fetched and
written to system memory at the end of every block transfer if the Write Back column entry is "Yes," DMAH_CHx_CTL_WB_EN = True,
DMAH_CHx_STAT_DST = True, and CFGx.DS_UPD_EN is enabled.
9.4.3.2 Auto-Reloading of Channel Registers
During auto-reloading, the channel registers are reloaded with their initial values at the completion of each block and the new values used for
the new block. Depending on the row number in Table 9-19, some or all of the SARx, DARx, and CTLx channel registers are reloaded from their
initial value at the start of a block transfer.
9.4.3.3 Contiguous Address between Blocks
In this case, the address between successive blocks is selected as a continuation from the end of the previous block.
3
This column assumes that the configuration parameter DMAH_CHx_CTL_WB_EN = True. If DMAH_CHx_CTL_WB_EN = False, then there is never writeback of the control
and status registers regardless of transfer type, and all rows of this column are "No".
User Manual
Table 9-19 Programming of transfer types and channel register update method
LLP_SRC_ RELOAD_SR
EN (CTLx) C (CRGx)
0 0
0 0
0 1
0 1
0 0
0 0
0 1
1 0
1 0
1 0
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LLP_DST_ RELOAD_DS CTLx, LLPx
EN (CTLx) T (CRGx) Update
Method
0 0 None, user
reprograms
0 1 CTLx, LLPx are
reloaded from
initial values
0 0 CTLx, LLPx are
reloaded from
initial values
0 1 CTLx, LLPx are
reloaded from
initial values
0 0 None, user
reprograms
1 0 CTLx, LLPx
loaded from
next Linked
List item
1 0 CTLx, LLPx
loaded from
next Linked
List item
0 0 CTLx, LLPx
loaded from
next Linked
List item
0 1 CTLx, LLPx
loaded from
next Linked
List item
1 0 CTLx, LLPx
loaded from
next Linked
List item
174
Ameba-D User Manual
SARx DARx Write
Update Update Back
Method Method
None None No
(Single) (Single)
Contiguous Auto-Reload No
Auto-Reload Contiguous No
Auto-Reload Auto-Reload No
None None Yes
(Single) (Single)
Contiguous Linked List Yes
Auto-Reload Linked List Yes
Linked List Contiguous Yes
Linked List Auto-Reload Yes
Linked List Linked List Yes
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