Realtek Ameba-D RTL872 D Series User Manual page 265

31 30 ...
RSVD
Bit Name Access
31:12 RSVD N/A
11 NULL_DATA R/W
10 RESTART R/W
9 STOP R/W
8 CMD R/W
7:0 DAT R/W
13.3.2.6 IC_SS_SCL_HCNT

Name: Standard Speed I

Size: 32 bits

Address offset: 0x14

Read/write access: read/write
31 30 29
Bit Name
31:16 RSVD
15:0 IC_SS_SCL_HCNT
User Manual
13 12 11
NULL_DATA
R/W
Reset Description
- Reserved
0x0 This bit controls whether to transfer slave address only. When this bit is set to 1, I
ignore REG_IC_TAR but take the TXFIFO data as slave address. It would only send TXFIFO
data in address phase without any further transmission.

1: Send TXFIFO data as slave address.

0: Normal operation. This bit will NOT influence any transfer sequence.
0x0 This bit controls whether a RESTART is issued before the byte is sent or received.

1: If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received
(according to the value of CMD), regardless of whether or not the transfer direction is
changing from the previous command.

0: If IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
0x0 This bit controls whether a STOP is issued after the byte is sent or received.

1: STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If
the Tx FIFO is not empty, the master immediately tries to start a new transfer by
issuing a START and arbitrating for the bus.

0: STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty.
If the Tx FIFO is not empty, the master continues the current transfer by
sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is
empty, the master holds the SCL line low and stalls the bus until a new command is
available in the Tx FIFO.
0x0 This bit controls whether a read or a write is performed. This bit does not control the
direction when the I

1: Read

0: Write
When a command is entered in the Tx FIFO, this bit distinguishes the write and read
commands. In slave-receiver mode, this bit is a "don't care" because writes to this register
are not required. In slave-transmitter mode, a "0" indicates that the data in IC_DATA_CMD is
to be transmitted.
0x0 This register contains the data to be transmitted or received on the I
to this register and want to perform a read, bits 7:0 (DAT) are ignored by the I
when you read this register, these bits return the value of data received on the I
2 C Clock SCL High Count Register
... 18 17
RSVD
Access Reset Description
N/A - Reserved
R/W 0x190 This register must be set before any I
I/O timing. This register sets the SCL clock high-period count for standard speed.
This register can be written only when the I
to the IC_ENABLE register being set to 0. Writes at other times have no effect.
All information provided in this document is subject to legal disclaimers.
10 9 8
RESTART STOP CMD
R/W R/W R/W
2
C acts as a slave. It controls only the direction when it acts as a master.
16 15 14
2 C bus transaction can take place to ensure proper
265
Inter-integrated Circuit (I2C) Interface
7 6 ...
DAT
R/W
2
C bus. If you are writing
13 ... 2
IC_SS_SCL_HCNT
R/W
2 C interface is disabled which corresponds
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1 0
2 C would
2 C. However,
2 C interface.
1 0