Realtek Ameba-D RTL872 D Series User Manual page 274


Address offset: 0x64

Read/write access: read-only
31 30
Bit Name Access
31:1 RSVD N/A
0 CLR_START_DET R
13.3.2.27 IC_CLR_GEN_CALL

Name: Clear GEN_CALL Interrupt Register

Size: 32 bits

Address offset: 0x68

Read/write access: read-only
31 30
Bit Name Access
31:1 RSVD N/A
0 CLR_GEN_CALL R
13.3.2.28 IC_ENABLE

Name: I 2 C Enable Register

Size: 32 bits

Address offset: 0x6C

Read/write access: read/write
31 30
Bit Name Access
31:2 RSVD N/A
1 ABORT R/W
0 ENABLE R/W
13.3.2.29 IC_STATUS

Name: I 2 C Status Register

Size: 32 bits

Address offset: 0x70

Read/write access: read-only
User Manual
29 ...
RSVD
Reset Description
- Reserved
0x0 Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.
29 ...
RSVD
Reset Description
- Reserved
0x0 Read this register to clear the GEN_CALL interrupt (bit 11) of the IC_RAW_INTR_STAT register.
29 ...
RSVD
Reset Description
- Reserved
Abort I 2 C current transfer without flush Tx/Rx FIFO
0x0 Controls whether the I

2
0: Disables I C (Tx and Rx FIFOs are held in an erased state)

1: Enables I 2 C
Software can disable I
that I 2 C is disabled properly.
When I 2 C is disabled, the following occurs:

The Tx FIFO and Rx FIFO get flushed.

Status bits in the IC_INTR_STAT register are still active until I
All information provided in this document is subject to legal disclaimers.
3
3
4 3
2 C is enabled.
2 C while it is active. However, it is important that care be taken to ensure
274
Ameba-D User Manual
2 1
CLR_START_DET
2 1
2 1
ABORT
R/W
2
C goes into IDLE state.
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0
R
0
CLR_GEN_CALL
R
0
ENABLE
R/W