Realtek Ameba-D RTL872 D Series User Manual page 148

16 LOCK_CH
15:14 LOCK_B_L
13:12 LOCK_CH_L
11 HS_SEL_SRC
10 HS_SEL_DST
9 FIFO_EMPTY
8 CH_SUSP
7:5 CH_PRIOR
4:0 RSVD
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R/W 0x0
R/W 0x0
R/W 0x0
N/A 0x1
R/W 0x1
R/W 0x1
R/W 0x0
R/W Channel Number.
For example:
Chan0=0
Chan1=1
N/A 0x0
Table 9-18 PROTCTL field to HPROT mapping
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Channel Lock Bit. When the channel is granted control of the master bus
interface and if the CFGx.LOCK_CH bit is asserted, then no other channels
are granted control of the master bus interface for the duration specified in
CFGx.LOCK_CH_L. Indicates to the master bus interface arbiter that this
channel wants exclusive access to the master bus interface for the duration
specified in CFGx.LOCK_CH_L.
This field does not exist if the configuration parameter
DMAH_CHx_LOCK_EN is set to False; in this case, the read-back value is
always 0.
Bus Lock Level. Indicates the duration over which CFGx.LOCK_B bit applies.
00 = Over complete DMA transfer
01 = Over complete DMA block transfer
1x = Over complete DMA transaction
This field does not exist if the parameter DMAH_CHx_LOCK_EN is set to
False; in this case, the read-back value is always 0.
Channel Lock Level. Indicates the duration over which CFGx.LOCK_CH bit
applies.
00 = Over complete DMA transfer
01 = Over complete DMA block transfer
1x = Over complete DMA transaction
This field does not exist if the configuration parameter
DMAH_CHx_LOCK_EN is set to False; in this case, the read-back value is
always 0.
Source Software or Hardware Handshaking Select. This register selects
which of the handshaking interfaces – hardware or software – is active for
source requests on this channel.
0 = Hardware handshaking interface. Software-initiated transaction
requests are ignored.
1 = Software handshaking interface. Hardware-initiated transaction
requests are ignored.
If the source peripheral is memory, then this bit is ignored.
Destination Software or Hardware Handshaking Select. This register selects
which of the handshaking interfaces – hardware or software – is active for
destination requests on this channel.
0 = Hardware handshaking interface. Software-initiated transaction
requests are ignored.
1 = Software handshaking interface. Hardware- initiated transaction
requests are ignored.
If the destination peripheral is memory, then this bit is ignored.
Indicates if there is data left in the channel FIFO. Can be used in conjunction
with CFGx.CH_SUSP to cleanly disable a channel.
1 = Channel FIFO empty
0 = Channel FIFO not empty
Channel Suspend. Suspends all DMA data transfers from the source until
this bit is cleared. There is no guarantee that the current transaction will
complete. Can also be used in conjunction with CFGx.FIFO_EMPTY to cleanly
disable a channel without losing any data.
0 = Not suspended.
1 = Suspend DMA transfer from the source.
Channel priority. A priority of 7 is the highest priority, and 0 is the lowest.
This field must be programmed within the following range:
0: (DMAH_NUM_CHANNELS – 1)
A programmed value outside this range will cause erroneous behavior.
Reserved
HPROT[0]
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Ameba-D User Manual
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