Realtek Ameba-D RTL872 D Series User Manual page 281

6 DMODE_STOP
5 DMODE_CMD
4:1 RSVD
0 DMODE_ENABLE
13.3.2.42 IC_DMA_DATA_LEN

2
Name: I C DMA Mode Transfer Data Length Register

Size: 32 bits

Address offset: 0xA4

Read/write access: read/write
31 30 29
DMA_DATA_TRD_LEN
Bit Name
31:16 DMA_DATA_TRD_LEN
15:0 DMA_DATA_LEN
13.3.2.43 IC_DMA_MODE

2
Name: I C DMA Mode Register

Size: 32 bits

Address offset: 0xA8

Read/write access: read/write
31 30
Bit Name
31:2 RSVD
1:0 DMA_MODE
13.3.2.44 IC_SLEEP

2
Name: I C Sleep Mode Register

Size: 32 bits

Address offset: 0xAC

Read/write access: read/write
31 30
User Manual
1: a RESTART is issued after the data is sent/received (according to the value of CMD_RW),
regardless of whether or not the transfer direction is changing from the previous
command.
R/W 0x0 This bit controls whether a STOP is issued after the byte is sent or received in DMA mode.

1: STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If
the Tx FIFO is not empty, the master immediately tries to start a new transfer by
issuing a START and arbitrating for the bus.

0: STOP is not issued after this byte.
R/W 0x0 This bit controls whether a read or write is performed in DMA mode. This bit does not
control the direction when the I
acts as a master.

1: Read

0: Write
N/A - Reserved
R/W 0x0 1: Set to enable DMA mode, clear when transfer is done
... 18 17
R
Access Reset Description
R 0x0 DMA mode transfer bytes
R/W 0x0 DMA transfer data length
29 ...
RSVD
Access Reset Description
N/A - Reserved
R/W 0x0 DMA Mode Select


29 ...
All information provided in this document is subject to legal disclaimers.
2
C acts as a slave. It controls only the direction when it
16 15 14
4 3
00: DMA legacy mode
01: DMA Control Register mode
4 3
281
Inter-integrated Circuit (I2C) Interface
13 ... 2
DMA_DATA_LEN
R/W
2 1
DMA_MODE
R/W
2 1
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