Realtek Ameba-D RTL872 D Series User Manual page 105

Direct Memory Access Controller (DMAC)
Fig 9-19 Breakdown of block transfer for DMAH_CH_FIFO_DEPTH = 8
The block transfer consists of six bursts of length 2 from the source, interleaved with six bursts – again of length 2 – to the destination, as
shown in Fig 9-17. The channel FIFO is alternatively filled by a burst from the source and emptied by a burst to the destination, until the block
transfer has completed. In this example, a transfer of each source or destination burst transaction is made up of two bursts, each of length 2.
Therefore, Example 2 has twice the number of bursts per block than Example 1.
Recommendation: To allow a burst transaction to complete in a single burst, the DMAC channel FIFO depth should be large enough to accept
an amount of data equal to an entire burst transaction. Therefore, in order to allow both source and destination burst transactions to complete
in one burst:
DMAH_CHx_FIFO_DEPTH >= max(2*src_burst_size_bytes, 2*dst_burst_size_bytes) (12)
Adhering to the above recommendation results in a reduced number of bursts per block, which in turn results in improved bus utilization and
lower latency for block transfers.
9.2.8.1.3 Example 3
Scenario: Effect of the maximum AMBA burst length, CFGx. MAX_ABRST. If the CFGx. MAX_ABRST = 2 parameter and all other parameters are
left unchanged from Example 1, Table 9-5, then the block transfer would look like that shown in Fig 9-20.
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