Realtek Ameba-D RTL872 D Series User Manual page 306

27:16 IR_TX_DUTY_NUM
15 RSVD
14 IR_TX_OUTPUT_INVERSE
13 IR_TX_DE_INVERSE
12:8 IR_TX_FIFO_LEVEL_TH
7 RSVD
6 IR_TX_IDLE_STATE
5 IR_TX_FIFO_OVER_INT_MASK
4 IR_TX_FIFO_OVER_INT_EN
3 IR_TX_FIFO_LEVEL_INT_MASK
2 IR_TX_FIFO_EMPTY_INT_MASK
1 IR_TX_FIFO_LEVEL_INT_EN
0 IR_TX_FIFO_EMPTY_INT_EN
15.3.2.2 IR_TX_SR

Name: IR Tx interrupt status register

Size: 32 bits

Address offset: 0x0008

Read/write access: read
31 30
15 14
IR_TX_FIFO_EMPTY IR_TX_FIFO_FULL
R R
7 6
RSVD
Bit Name
31:16 RSVD
15 IR_TX_FIFO_EMPTY
14 IR_TX_FIFO_FULL
13:8 IR_TX_FIFO_OFFSET
User Manual
R/W 0x0 Duty cycle setting for modulation frequency
For example: for 1/3 duty cycle, IR_DUTY_NUM = (IR_DIV_NUM+1)/3
N/A 0x0 Reserved

R/W 0x0 0: Not inverse active output

1: Inverse active output

R/W 0x0 0: Not inverse FIFO define

1: Inverse FIFO define
R/W 0x0 Tx FIFO interrupt threshold is from 0 to 15.
When Tx FIFO depth = < threshold value, interrupt is triggered.
N/A 0x0 Reserved
R/W 0x0 Tx output state in idle

0: Low

1: High
R/W 0x0 Tx FIFO overflow interrupt

0: Unmask

1: Mask
R/W 0x0 Tx FIFO overflow interrupt

0: Disable

1: Enable
R/W 0x0 Tx FIFO level interrupt

0: Unmask

1: Mask
R/W 0x0 Tx FIFO empty interrupt

0: Unmask

1: Mask
R/W 0x0 Tx FIFO level interrupt
When Tx FIFO offset = < threshold value, interrupt is triggered.

0: Disable

1: Enable
R/W 0x0 Tx FIFO empty interrupt

0: Disable

1: Enable
29 ...
RSVD
13 12
5 4
IR_TX_STATUS
R
Access Reset Description
- 0 Reserved

R 0


R 0

R 0 Tx FIFO offset is from 0 to 32.
All information provided in this document is subject to legal disclaimers.
306
18
11 10
IR_TX_FIFO_OFFSET
R
3 2
IR_TX_FIFO_OVE
RSVD R_INT_STATUS
R
0: Not empty
1: Empty
0: Not full
1: Full
Ameba-D User Manual
17 16
9 8
1 0
IR_TX_FIFO_LEVE IR_TX_FIFO_EMP
L_INT_STATUS TY_INT_STATUS
R R
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