Realtek Ameba-D RTL872 D Series User Manual
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Realtek Ameba-D RTL872 D Series User Manual

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Table of Contents

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UM0400
Ameba-D User Manual
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com

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Summary of Contents for Realtek Ameba-D RTL872 D Series

  • Page 1 UM0400 Ameba-D User Manual Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com...
  • Page 2 Realtek products, reference designs or services are used. Information published by Realtek regarding third party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of the Realtek’s reference designs or other items may require a license from a third party under the patents or other intellectual property of the third party, or a license from Realtek under the patents or other intellectual property of Realtek.
  • Page 3 Ameba-D User Manual TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.

  • Page 4: Table Of Contents

    ISER0 and ISER1 ................................39 4.4.2 ICER0 and ICER1 ................................40 4.4.3 ISPR0 and ISPR1 ................................40 4.4.4 ICPR0 and ICPR1 ................................40 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 5 Data and Control Flow ..............................59 8.2.2 Interrupts ..................................61 Registers ....................................69 8.3.1 Bus Interface ................................. 69 8.3.2 Register Memory Map ..............................70 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 6 Functional Description ..............................196 10.3 PWM Mode Timer ................................198 10.3.1 Introduction ................................198 10.3.2 Features ..................................198 10.3.3 Block Diagram ................................199 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 7 C) Interface ........................... 245 13.1 Introduction ................................... 245 13.2 Functional Description ..............................245 13.2.1 Overview ..................................245 13.2.2 C Terminology ................................246 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 8 Infrared Radiation (IR) ..............................302 15.1 Overall Description ................................ 302 15.1.1 Introduction ................................302 15.1.2 Features ..................................303 15.2 Architecture ................................... 303 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 9 Audio Output ................................333 17.5.2 Audio Input ................................. 334 17.6 Registers ..................................337 17.6.1 Analog Part ................................. 337 17.6.2 Digital Part.................................. 341 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 10 RGB DMA Auto-mode ..............................451 20.4.2 MCU DMA Trigger-mode ............................452 20.4.3 MCU I/O Mode ................................452 Quadrature Decoder (Q-Decoder) ..........................453 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 11 22.5.10 Rx Page Own Bit Register (IS_RX_PAGE_OWNx) ....................489 22.5.11 Version ID (IS_VERSION_ID) ............................ 489 Abbreviations ..................................490 Revision History..................................494 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 12: List Of Tables

    Fig 9-21 Channel FIFO contents at times indicated in Fig 9-20 ......................106 Fig 9-22 Breakdown of block transfer where max_abrst = 2, Case 2 ....................107 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 13 Fig 10-13 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) ............... 204 Fig 10-14 Edge-aligned PWM waveforms (ARR=8, CCxP=0) ......................205 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 14 Fig 16-9 Shadow key condition ................................ 320 Fig 16-10 Correct three-key condition ............................. 321 Fig 17-1 Audio codec diagram ................................329 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 15 Fig 20-20 RGB I/F 16-bit output ............................... 430 Fig 20-21 LED interface ..................................431 Fig 20-22 LED control timing ................................432 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 16 Fig 22-18 FIFO allocation of 5.1 channel (sample bit = 24-bit) ......................482 Fig 22-19 FIFO allocation of 5.1 channel (sample bit = 32-bit) ......................482 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 17: List Of Figures

    Fig 9-21 Channel FIFO contents at times indicated in Fig 9-20 ......................106 Fig 9-22 Breakdown of block transfer where max_abrst = 2, Case 2 ....................107 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 18 Fig 10-13 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) ............... 204 Fig 10-14 Edge-aligned PWM waveforms (ARR=8, CCxP=0) ......................205 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 19 Fig 16-9 Shadow key condition ................................ 320 Fig 16-10 Correct three-key condition ............................. 321 Fig 17-1 Audio codec diagram ................................329 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 20 Fig 20-20 RGB I/F 16-bit output ............................... 430 Fig 20-21 LED interface ..................................431 Fig 20-22 LED control timing ................................432 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 21 Fig 22-18 FIFO allocation of 5.1 channel (sample bit = 24-bit) ......................482 Fig 22-19 FIFO allocation of 5.1 channel (sample bit = 32-bit) ......................482 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 22: Conventions

    Hardware will automatically clear to 0 when software has written to this bit. Used for the reserved bit which should not be concerned by users. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 23: Product Overview

    KM0 CPU SGPIO (One Wire Communication) HS_TIM x4 @ 32KHz RSIP (Flash Decryption) HS_WDT Low Power Peripherals Timer Fig 1-1 System architecture User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 24 CPU and the DMA controller, and also for peripherals on the asynchronous bridge to have a fixed clock that doesn't track the system clock. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 25: Memory Organization

    IDAU 0x0200_0000 0x07FF_FFFF 96MB HS_SYSON Non-Secure 0x4000_0000 0x4000_0FFF Secure 0x5000_0000 0x5000_0FFF HS_TIM0 ~ 3/4/5 Non-Secure 0x4000_2000 0x4000_2FFF HS_UART0 Non-Secure 0x4000_4000 0x4000_4FFF User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 26: Km0 Memory Map And Register Boundary Addresses

    RXI300_KM0 0x4801_8000 0x4801_8FFF SGPIO 0x4801_A000 0x4801_AFFF Cap-Touch/ADC/Comparator 0x4801_C000 0x4801_CFFF Q-Decoder 0x4801_E000 0x4801_EFFF Flash Controller 0x4808_0000 0x4808_0FFF Flash Memory 0x0800_0000 0x0FFF_FFFF 128MB User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 27: Km4 Embedded Sram

    It accelerates code execution with a system of instruction prefetch and cache lines. PSRAM 4MB 8IO DDR PSRAM is included in Ameba-D, up to 50MHz DDR. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 28: Memory Protection Unit (Mpu)

    Privileged access is permitted only. Unprivileged access generates a BusFault.  This register is word accessible only. Half-word and byte accesses are unpredictable.  Configurations: This register is always implemented. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 29: Mpu_Ctrl

    MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 30: Mpu_Rnr

    Preface: This register provides access to the configuration of the MPU region selected by MPU_RNR.REGION for the appropriate security state. The field description applies to the currently selected region. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 31: Mpu_Rlar

    Enable. Region enable.  0: Region is disabled.  1: Region is enabled. This bit resets to 0 on a Warm reset. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 32: Mpu_Rbar_A

    This register is word accessible only. Half-word and byte accesses are unpredictable.  Configurations:  Present only if the Main Extension is implemented.  Reserved if the Main Extension is not implemented. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 33: Mpu_Mair0

    This field resets to an unknown value on a Warm reset. 23:16 ATTR2 Memory attributes encoding for MPU regions with an AttrIndx of 2. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 34: Mpu_Mair1

    Purpose: Defines the memory attribute encoding for use in the MPU_MAIR0 and MPU_MAIR1 register.  Usage constraints: None.  Configurations: All. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 35: Outer

    11RW: Normal memory, Inner Write-Back Non-transient. Note: R and W specify the outer read and write allocation policy.  0: Don’t allocate  1: Allocate User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 36: Nested Vectored Interrupt Controller (Nvic)

    Do not call RTOS _ISR functions from any interrupt that has a higher priority than this macro. Table 4-1 NVIC table User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 37 KM0 LGDMA0_Channel0 interrupt  LGDMA0_Channel1 KM4 USB interrupt  KM0 LGDMA0_Channel1 interrupt  SDIO_DEV LGDMA0_Channel2 KM4 SDIO_DEV interrupt  KM0 LGDMA0_Channel2 interrupt User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 38: Nvic Register Description

    This register allows disabling interrupts and reading back the interrupt enabled state for peripheral functions. ICER1 0x184 Interrupt Clear Enable Register 1. See ICER0 description. ISPR0 0x200 Interrupt Set Pending Register 0. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 39: Iser0 And Iser1

    Write: Writing 0 has no effect, writing 1 enables the interrupt.  Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 40: Icer0 And Icer1

    The interrupt number to be programmed in the STIR register is listed in Table 4-3. Table 4-3 Software trigger interrupt register Address Offset Name Description User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 41 Reserved. Read value is undefined, only 0 should be written. INTID Writing a value to this field generates an interrupt for the specified interrupt number. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 42: Cpu System Tick (Systick) Timer

    This register contains control information for the SysTick timer and provides a status flag. It is a part of the CPU, and determines the clock source for the SysTick timer. … COUNTFLAG RSVD User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 43: Syst_Rvr

    This register returns the current count from the SysTick counter when it is read by software. … … CURRENT RSVD Name Access Reset Description 31:24 RSVD Reserved. Read value is undefined, only zero should be written. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 44: Syst_Calib

    23:0 TENMS This field is loaded 0 from the SYST_CALIB register in SYSCON, and always RAZ/WI (read as zero, write ignored). User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 45: Pad Control And Pinmux

    Fig 6-1 Pad diagram 6.2.1 Pad Types The pad types of Ameba-D are listed in Table 6-1. Table 6-1 Pad types User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 46: Pad Pull Resistor Control

    PUPDC = x and PU = 0 and PD = 0 No pull PUPDC = 0 and PU = 1 10k pull-up PUPDC = 1 and PU = 1 4.7k pull-up User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 47: Pad Schmitt Trigger

    When audio function is not used, it is necessary to set AVCC to 3V above and use these pins as normal GPIO, as Table 6-5 shows. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 48: Pin Multiplexing Function

    Each I/O pin has a multiplexer with up to 32 alternate function inputs (AF0 to AF31) that can be configured through the PADCTRL register. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 49: Register − Padctrl

    Each I/O pin has one PADCTRL register assigned to control the pin’s electrical characteristics. RSVD RSVD PAD_BIT_SHUT_ PAD_BIT_SDIO_ PAD_BIT_SCHMI PAD_BIT_PULL_DO PAD_BIT_PULL_UP PAD_BIT_DRIVING_STRENGTH DOWN H3L1 RSVD TT_TRIGGER_EN WN_RESISTOR_EN _RESISTOR_EN PAD_BIT_FUNCTION_ID RSVD Address Name Access Description User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 50 Controls “PD” signal, pull-down resistor enable, resister is 50kohm. PAD_BIT_PULL_UP_RESISTOR_EN Controls “PU” signal, pull-up resistor enable, resister is 50kohm. RSVD Reserved for function ID extension PAD_BIT_FUNCTION_ID Function ID User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 51: Inter Processor Communication (Ipc)

    IPC1_ISR register, the KM0 CPU is acknowledged by writing a ‘1’ to bit[2] of the IPC1_ICR register, which in turn, clears bit[2] of the IPC1_ISR register, enables KM4 to send another message. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 52: Hardware Semaphore

    KM4 writes a ‘1’ to IPC0_SEM[0], hardware helps to clear the CPUID and ‘Free’ bit, so that another CPU can get this semaphore if needed. you can give interrupt (IPCx_IRR) to peer CPU for the semaphore free. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 53: Ipc Registers

    IPC_IERx Writing a ‘1’ to a bit of this register enables the corresponding interrupt.  Writing a ‘0’ has no effect. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 54: Ipcx_Idr

    IPC_ICRx Writing a ‘1’ to a bit of this register clears the corresponding interrupt.  Writing a ‘0’ has no effect. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 55: Ipc0_Cpuid

    Refer to the description of the IPC_SEM_CPUID0 bit. IPC_SEM_FREEF Refer to the description of the IPC_SEM_FREE0 bit. IPC_SEM_CPUIDE Refer to the description of the IPC_SEM_CPUID0 bit. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 56: Ipcx_Ier_R

    Access Default Description  31:0 IPC_IERx_R 1: Interrupt is enabled for this bit.  0: Interrupt is disabled for this bit. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 57: Ipc_Usr

    These are user-defined register, and can be used for H2L/L2H command defined by user. … User-defined Name Access Default Description 31:0 User-defined These registers can be used for H2L/L2H command defined by user. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 58: General Purpose Input/Output (Gpio)

    Configurable reset values on output signals  Configurable synchronization of interrupt signals Functional Description This chapter describes the functional operation of the GPIO. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 59: Data And Control Flow

    When a signal is configured for software control, the data and direction control for the signal are sourced from the data register (gpio_swportx_dr) and direction control register (gpio_swportx_ddr), where x is a. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 60 APB. The assumption is that the APB bridge does not lose ownership of the AHB during consecutive accesses when PCLK=HCLK. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 61: Interrupts

    Fig 8-4 illustrates how the interrupts are generated and how the data flows. The signal names in the diagram correspond to either I/O signals or memory-mapped registers. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 62: Fig 8-4 Interrupt Rtl Block Diagram

    Fig 8-5 Debounce RTL diagram User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 63: Fig 8-6 Debounce Timing With Asynchronous Reset Flip-Flops

    Single Edge Fig 8-7 shows an RTL diagram of the synchronization and edge detection of interrupt sources on gpio_ext_portaN signals, when GPIO_INT_BOTH_EDGE=0. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 64: Fig 8-7 Synchronization And Edge Detect Interrupt Generation When Gpio_Int_Both_Edge=0

    It also shows how an interrupt is cleared by a write to the interrupt clear register. Fig 8-8 Interrupt edge detection and interrupt clear timing when GPIO_SYNC_PA_INTERRPUTS = 1 (metastability included) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 65: Fig 8-9 Interrupt Edge Detection And Interrupt Clear Timing When Gpio_Sync_Pa_Interrputs = 0 (Metastability Removed)

    In this example, the write to the interrupt clear register does not clear the second interrupt, and the gpio_intr{_n} signal is not de-asserted. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 66: Fig 8-10 Write To Interrupt Clear Register, Coincident With Detection Of New Interrupt

    Fig 8-11 shows the synchronization and edge detect interrupt generation of the interrupt sources on gpio_ext_portaN signals when GPIO_INT_BOTH_EDGE = 1. Fig 8-11 Synchronization and edge detect interrupt generation when GPIO_INT_BOTH_EDGE=0 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 67: Fig 8-12 Interrupt Edge Detection And Interrupt Clear Timing When Gpio_Sync_Pa_Interrputs = 1 And Gpio_Int_Both_Edge=1 (Metastability Included)

    (metastability included) Fig 8-13 shows a timing diagram similar to Fig 8-12, except that in this scenario, metastability registers are removed. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 68: Fig 8-13 Interrupt Edge Detection And Interrupt Clear Timing When Gpio_Sync_Pa_Interrputs = 0 And

    Fig 8-14 shows the generation of level-sensitive interrupts. As for edge-detect interrupts, the user can configure GPIO with or without debounce logic. Fig 8-14 Level-sensitive interrupt RTL diagram User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 69: Registers

    Fig 8-16 shows the read/write busses between the APB and the APB slave. Fig 8-16 Relationship between APB and APB slave data widths User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 70: Register Memory Map

    Interrupt mask register Width: GPIO_PWIDTH_A Reset Value: 0x0 gpio_inttype_level 0x38 Interrupt level register Width: GPIO_PWIDTH_A Reset Value: 0x0 gpio_int_polarity 0x3c Interrupt polarity register User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 71: Register And Field Descriptions

    The following sections contain the memory diagrams and field descriptions for the individual registers. 8.3.3.1 gpio_swporta_dr  Name: Port A Data Register  Size: GPIO_PWIDTH_A  Address offset: 0x00  Read/write access: read/write User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 72 The default source is configurable 0:GPIO_PWIDTH_A-1 through the GPIO_DFLT_SRC_A configuration parameter. (See above) 0 – Software mode (default) 1 – Hardware mode User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 73 GPIO_DFLT_DIR_B parameter. 0 – Input (default) 1 – Output Reset Value: GPIO_DFLT_DIR_B 8.3.3.6 gpio_swportb_ctl  Name: Port B Data Source  Size: User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 74 Reset Value: GPIO_SWPORTC_RESET 8.3.3.8 gpio_swportc_ddr  Name: Port C Data Direction  Size: GPIO_PWIDTH_C  Address offset: 0x1C  Read/write access: read/write User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 75 {GPIO_PWIDTH_C{GPIO_DFLT_SRC_C in each bit}}. 8.3.3.10 gpio_swportd_dr  Name: Port D Data Register  Size: GPIO_PWIDTH_D  Address offset: 0x24  Read/write access: read/write User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 76 1 bit wide if GPIO_PORTD_SINGLE_CTL = 1  GPIO_PWIDTH_D bits wide if GPIO_PORTD_SINGLE_CTL = 0  Address offset: 0x2C  Read/write access: read/write Name Access Description User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 77  Read/write access: read/write This register is available only if Port A is configured to generate interrupts (GPIO_PORTA_INTR = Include (1)). User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 78 Port A. Whenever a 0 is written to a bit of this register, it configures the interrupt type to falling-edge or active-low sensitive; otherwise, it is rising-edge or active-high sensitive. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 79 This register is available only if Port A is configured to generate interrupts (GPIO_PORTA_INTR = Include (1)) and when the debounce logic is included (GPIO_DEBOUNCE = Include (1)). User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 80 Name: External Port A  Size: GPIO_PWIDTH_A  Address offset: 0x50  Read/write access: read Name Access Description 31:GPIO_PWIDTH_A Reserved Read as zero Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 81 Name: External Port D  Size: GPIO_PWIDTH_D  Address offset: 0x5C  Read/write access: read Name Access Description 31:GPIO_PWIDTH_D Reserved Read as zero Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 82 This register is available only if Port A is configured to generate interrupts (GPIO_PORTA_INTR = Include (1)) and interrupt detection is configured to generate on both rising and falling edges of external input signal (GPIO_INT_BOTH_EDGE=Include (1)). Interrupt bothedge User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 83 The value of this register is derived from the GPIO_ID configuration parameter. 0 = Exclude 1 = Include ADD_ENCODED_PARAMS The value of this register is derived from the GPIO_ADD_ENCODED_PARAMS configuration parameter. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 84 The value of this register is derived from the GPIO_APB_DATA_WIDTH configuration parameter. 0x0 = 8 bits 0x1 = 16 bits 0x2 = 32 bits 0x3 = Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 85: Programming The Gpio

    When reading back registers that are no longer present due to configuration parameters settings, then 0 is read back. For example, if APB_DATA_WITDH = 32 bits and GPIO_PWIDTH_A = 8, then the top 24 bits read back 0. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 86: Direct Memory Access Controller (Dmac)

    B is handled by the DMAC. The channel source and destination arbitrate independently for the AHB master interface, along with other channels. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 87: Fig 9-2 Peripheral-To-Peripheral Dma Transfer On The Same Ahb Layer

    DMA transfer between a source and destination on different AHB layers. Peripheral B uses a hardware handshaking interface. The memory does not use any handshaking interface to the DMAC in order to initiate DMA transfers. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 88: Basic Definitions

    This interface is used to request, User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 89: Fig 9-4 Dma Transfer Hierarchy For Non-Memory Peripherals

    Note: For memory peripherals, there is no DMA Transaction Level. Fig 9-4 DMA Transfer Hierarchy for Non-Memory Peripherals Fig 9-5 DMA transfer hierarchy for memory User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 90: Features

     Up to eight channels, one per source and destination pair  Unidirectional channels – data transfers in one direction only User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 91 Handshaking interfaces for source and destination peripherals (up to16)  Hardware handshaking interface (software handshaking interface not supported)  Peripheral interrupt handshaking interface User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 92: Functional Description

    DMAC Memory to Peripheral DMAC Memory to Peripheral Peripheral Peripheral to Memory DMAC Peripheral to Memory Peripheral Peripheral to Peripheral DMAC User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 93: Handshaking Interface

    (block size) of source transfer width (CTLx.SRC_TR_WIDTH) to be transferred by the DMAC in a block transfer; this is programmed into the CTLx.BLOCK_TS field. Therefore, the total number of bytes to be transferred in a block is: User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 94: Memory Peripherals

    If: blk_size_bytes/src_burst_size_bytes = integer then the source never enters this region, and the source block uses only burst transactions. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 95 Fig 9-6 illustrates the hardware handshaking interface between a peripheral – whether a destination or source – and the DMAC when the peripheral is not the flow controller. Fig 9-6 Hardware handshaking interface User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 96: Fig 9-7 Burst Transaction - Pclk = Hclk

    Single Transaction Region, and therefore the DMAC does not sample dma_single[0]. The handshaking loop is as follows: Fig 9-7 Burst transaction – pclk = hclk User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 97 The dma_req signal should be de-asserted when dma_ack is asserted, even if the condition that generates dma_req in the peripheral is True. Fig 9-9 shows a single transaction that occurs in the Single Transaction Region. The handshaking loop is as follows: User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 98: Fig 9-10 Burst Followed By Back-To-Back Single Transactions

    In Fig 9-11, an active level on dma_req[0] after time T4 takes precedence over the active level on dma_single[0] after time T3. Fig 9-11 Early-Terminated burst transaction User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 99: Fig 9-12 Burst Transaction Ignored During Active Single Transaction

    13 is asserted when the destination FIFO has at least one free location. The burst_flag signal in Fig 9-13 is asserted when the destination FIFO contains free locations greater than or equal to some watermark-level number. Fig 9-13 Generation of dma_req and dma_single by source User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 100: Handshaking Interface - Peripheral Is Flow Controller

    Fig 9-14 shows the hardware handshaking interface between a destination or source peripheral and the DMAC when the peripheral is the flow controller. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 101: Fig 9-15 Burst Transaction Followed By Single Transaction That Terminates Block

    Fig 9-15 Burst transaction followed by single transaction that terminates block User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 102: Setting Up Transfers

    Source burst transaction length CTLx.DEST_MSIZE Destination burst transaction length CFGx.MAX_ABRST Maximum AMBA burst length CFGx.FIFO_MODE FIFO mode select CFGx.FCMODE Flow-control mode User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 103 4 from the source, interleaved with three bursts, again of length 4, to the destination. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 104: Fig 9-17 Breakdown Of Block Transfer

    With the DMAH_CHx_FIFO_DEPTH parameter set to 8 bytes instead of 16 bytes, the block transfer would look like that shown in Fig 9-19. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 105 Scenario: Effect of the maximum AMBA burst length, CFGx. MAX_ABRST. If the CFGx. MAX_ABRST = 2 parameter and all other parameters are left unchanged from Example 1, Table 9-5, then the block transfer would look like that shown in Fig 9-20. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 106 FIFO locations are redundant for this block transfer. However, this is not the general case. The block transfer could proceed as indicated in Fig 9-22. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 107 Early-Terminated Burst Transaction. Table 9-6 lists the parameters used in this example. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 108: Fig 9-24 Breakdown Of Block Transfer

    Fig 9-24 Breakdown of block transfer Fig 9-25 shows the status of the source FIFO at various times throughout the source block transfer. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 109: Fig 9-26 Source Fifo Contents Where Watermark Level Is Dynamically Adjusted

    Under the same conditions, it is possible for software to complete a source block transfer without initiating single transactions from the source. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 110: Fig 9-27 Block Transfer To Destination

    12 - 8) left to transfer in the destination block. However, CTLx.DST_TR_WIDTH implies 64-bit AHB transfers to the destination (dst_single_size_bytes = 8 byte); therefore, the DMAC cannot form a single word of the specified CTLx.DST_TR_WIDTH. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 111 32 bits CTLx.DST_TR_WIDTH = 3’b010 32 bits CTLx.SRC_MSIZE = 3’b010 Decode value = 8 CTLx.DEST_MSIZE = 3’b001 Decode value = 4 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 112: Fig 9-28 Block Transfer Up To Time 'T4

    At time ‘t4’, a source burst transaction is requested, and the DMAC attempts a burst of length 4. Suppose that this burst is early-burst terminated after three AHB transfers. The FIFO status after this burst might look like that shown in Fig 9-30. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 113: Fig 9-30 Fifo Status After Early-Terminated Burst

    Table 9-9 Parameters in transfer operation – Example 7 Parameter Description CTLx.TT_FC = 3’b111 Peripheral-to-peripheral transfer with DMAC as flow controller CTLx.BLOCK_TS = x – User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 114: Fig 9-31 Data Loss When Pre-Fetching Is Enabled

    Consider the block transfer shown in Fig 9-31, where the destination is the flow controller and data pre-fetching is enabled (CFGx.FCMODE = 0). Fig 9-31 Data loss when pre-fetching is enabled User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 115: Fig 9-32 Timing Exception On Dma_Finish To Source Peripheral

    FIFO that are effectively lost. Case 2a – Data pre-fetching enabled but no data loss. Source enters Single Transaction Region when destination signals last transaction User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 116: Fig 9-33 Case Of No Data Loss When Pre-Fetching Is Enabled

    Therefore, the source enters the Single Transaction Region at time T6. At time T7, the DMAC samples that dma_single[0] from the source peripheral is asserted and initiates a single transaction. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 117 T1 and completes this burst request at time T4. Fig 9-35 Case where source does not enter single transaction region when destination asserts dma_last[1] User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 118 CTLx.DST_TR_WIDTH = 3’b010 32 bits CTLx.TT_FC = 3’b111 Peripheral to Peripheral transfer with destination as flow controller DMAH_CHx_FIFO_DEPTH = 32 bytes – User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 119: Fig 9-36 Data Loss When Data Pre-Fetching Is Disabled

    All other interface signals are ignored. This interface can be used where the slave peripheral does not have hardware handshaking signals. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 120: Flow Control Configurations

    Fig 9-38 indicates five different flow control configurations using hardware handshaking interfaces – a simplified version of the interface is shown. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 121: Peripheral Burst Transaction Requests

    For demonstration purposes, a receive SSI is used as a source peripheral, and a transmit SSI is used as a destination peripheral. Note: Throughout this section, SSI-related parameters are prefixed with “SSI”. DMAC-related parameters are prefixed with “DMA”. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 122 FIFO. This occurs because the DMAC has not had time to service the DMAC request before the SSI transmit FIFO becomes empty. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 123 Therefore, for optimal operation, DMA.CTLx.DEST_MSIZE should be set at the FIFO level that triggers a transmit DMAC request; that is: DMA.CTLx.DEST_MSIZE = SSI_TX_FIFO_DEPTH - SSI.DMATDLR (14) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 124: Fig 9-41 Ssi Receive Fifo

    Note: The SSI receive FIFO is not empty at the end of the source burst transaction if the SSI has successfully received one data item or more on the SSI serial receive line before the end of the burst, as illustrated in Fig 9-41. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 125: Generating Requests For The Ahb Master Bus Interface

    There is no handshaking mechanism employed between a memory peripheral and the DMAC. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 126 The destination is on the same AHB layer, but the channel is not currently in the middle of a transaction to the destination peripheral. The same rules apply when an end-of-destination transaction is signalled. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 127: Arbitration For Ahb Master Interface

    AHB bus, then AHB transfers can proceed between the peripheral and DMAC. Fig 9-42 illustrates the arbitration flow of the master bus interface. Fig 9-42 Arbitration flow for master bus interface User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 128: Scatter/Gather

    (SGRx.SGC) and destination scatter count (DSC), respectively, at the start of each block transfer. Fig 9-43 shows an example of a destination scatter transfer. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 129: Fig 9-43 Example Of Destination Scatter Transfer

    SARx = A0 (starting source address) Fig 9-44 shows a source gather when SGR.SGI = 0x01. Fig 9-44 Source gather when SGR.SGI = 0x1 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 130: Endianness

    User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 131: Registers

    Reg Exist: dnc ≥ 2 DAR1 0x060 Channel 1 Destination Address Register Reg Exist: dnc ≥ 2 LLP1 0x068 Channel 1 Linked List Pointer Register User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 132 Channel 3 Destination Status Address Register Reg Exist: dnc ≥ 4 and dstat3 = True CFG3 0x148 0x0000000400000e40 Channel 3 Configuration Register User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 133 Channel 6 Linked List Pointer Register Reg Exist: dnc ≥ 7 and llp6_hc = False CTL6 0x228 Configuration dependent Channel 6 Control Register User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 134 Reg Exist: Yes StatusBlock 0x2f0 Status for IntBlock Interrupt Reg Exist: Yes StatusSrcTran 0x2f8 Status for IntSrcTran Interrupt Reg Exist: Yes User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 135 The register exists when this parameter is set to True. DMA_COMP_P 0x3e0 Depends on user Refer to the bit table in the description for ARAMS_3 configuration DMA_COMP_PARAMS_3. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 136: Registers And Field Descriptions

    This is the DMAC Channel Enable Register. If software needs to set up a new channel, then it can read this register in order to find out which channels are currently inactive; it can then enable an inactive channel with the required priority. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 137 For information on how the SARx is updated at the start of each DMA block for multi-block transfers, refer to Table 9-19. dnc = DMAH_NUM_CHANNELS If dnc = 8, then this field is not present. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 138 (BLOCK_TS * SRC_TR_WIDTH)/DST_TR_WIDTH != integer (where SRC_TR_WIDTH, DST_TR_WIDTH is byte width of transfer) 9.3.2.2.4 LLPx  Name: Linked List Pointer Register for Channel x  Size: 64 bits (upper 32 bits are reserved) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 139 The CTLx register is part of the block descriptor (linked list item – LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 140 00 = AHB master 1 01 = AHB master 2 10 = AHB master 3 11 = AHB master 4 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 141 Dependencies: This field does not exist if DMAH_CHx_SRC_GAT_EN is not selected; in this case, the read-back value is always 0. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 142 This value must be less than or equal to DMAH_Mk_HDATA_WIDTH, where k is the AHB layer 1 to 4 where the destination resides. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 143 SSTAT3 – 0x128  SSTAT4 – 0x180  SSTAT5 – 0x1d8  SSTAT6 – 0x230  SSTAT7 – 0x288  Read/write access: read/write User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 144 Size: 64 bits (upper 32 bits are reserved)  Address offset: for x = 0 to 7:  SSTATAR0 – 0x030  SSTATAR1 – 0x088 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 145 LLI before the start of the next block. 9.3.2.2.10 CFGx  Name: Configuration Register for Channel x  Size: 64 bits (upper 32 bits are reserved) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 146 DSTATARx register, stored in the DSTATx register and written out to the DSTATx location of the LLI if DS_UPD_EN is high. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 147 This field does not exist if the configuration parameter DMAH_CHx_LOCK_EN is set to False; in this case, the read-back value is always 0. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 148 A programmed value outside this range will cause erroneous behavior. RSVD Reserved Table 9-18 PROTCTL field to HPROT mapping 1’b1 HPROT[0] User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 149 DSR5 – 0x208  DSR6 – 0x260  DSR7 – 0x2b8  Read/write access: read/write Destination Scatter register contains two fields: User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 150 Writing to the appropriate bit in the Clear registers clears an interrupt in the Raw Status registers and the Status registers on the same clock cycle. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 151 Access Reset Description 63:DMAH_NUM_CHANNELS RSVD Reserved DMAH_NUM_CHANNELS-1:0 STATUS Interrupt status. 9.3.2.3.3 MaskBlock, MaskDstTran, MaskErr, MaskSrcTran, MaskTfr  Name: Interrupt Mask Registers User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 152 ClearTfr[2] is the clear bit for the Channel 2 transfer complete interrupt. Writing a 0 has no effect. These registers are not readable. Name Access Reset Description 63:DMAH_NUM_CHANNELS RSVD Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 153 DMAC configuration has not optimized the same registers. In normal operation, the readback value of some registers is a function of the DMAC state and does not match the value written. Name Access Reset Description User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 154 The value of this register is derived from the DMAH_CH7_MULT_SIZE coreConsultant parameter. 0x0 = 4 0x1 = 8 0x2 = 16 0x3 = 32 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 155 The value of this register is derived from the DMAH_CH7_DTW coreConsultant parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 156 The value of this register is derived from the DMAH_CH5_MULT_SIZE coreConsultant parameter. 0x0 = 4 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 157 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 158 0x1 = TRUE CH6_LOCK_EN The value of this register is derived from the DMAH_CH6_LOCK_EN coreConsultant parameter. 0x0 = FALSE 0x1 = TRUE User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 159 Reserved 62:60 CH3_FIFO_DEPTH The value of this register is derived from the DMAH_CH3_FIFO_DEPTH coreConsultant parameter. 0x0 = 8 0x1 = 16 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 160 The value of this register is derived from the DMAH_CH3_SRC_GAT_EN coreConsultant parameter. 0x0 = FALSE 0x1 = TRUE CH3_DST_SCA_EN The value of this register is derived from the DMAH_CH3_DST_SCA_EN coreConsultant parameter. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 161 0x4 = NO_HARDCODE 18:16 CH4_MAX_MULT_SIZE The value of this register is derived from the DMAH_CH4_MULT_SIZE coreConsultant parameter. 0x0 = 4 0x1 = 8 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 162 The value of this register is derived from the DMAH_CH4_DTW coreConsultant parameter. 0x0 = NO_HARDCODE 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 163 0x1 = 8 0x2 = 16 0x3 = 32 0x4 = 64 0x5 = 128 0x6 = 256 0x7 = reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 164 0x6 = 256 0x7 = reserved RSVD Reserved 30:28 CH2_FIFO_DEPTH The value of this register is derived from the DMAH_CH2_FIFO_DEPTH coreConsultant parameter. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 165 0x1 = TRUE CH2_SRC_GAT_EN The value of this register is derived from the DMAH_CH2_SRC_GAT_EN coreConsultant parameter. 0x0 = FALSE 0x1 = TRUE User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 166 0x2 = RELOAD_CONT 47:44 CH7_MULTI_BLK_TYPE 0x3 = RELOAD_RELOAD 43:40 CH7_MULTI_BLK_TYPE 0x4 = CONT_LLP 39:36 CH7_MULTI_BLK_TYPE 0x5 = RELOAD_LLP 35:32 CH7_MULTI_BLK_TYPE 0x6 = LLP_CONT User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 167 0x1 = TRUE CH0_MULTI_BLK_EN The value of this register is derived from the DMAH_CH0_MULT_BLK_EN coreConsultant parameter. 0x0 = FALSE 0x1 = TRUE User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 168 Bits 63:32 include the top-level parameter for DMAC. Bits 31:0 include the maximum block size parameters for Channel 0 to Channel 7. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 169 The value of this register is derived from the DMAH_NUM_ CHANNELS coreConsultant parameter. 0x00 = 1 0x10 = 8 39:36 RSVD Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 170: Programming The Dmac

    Shipped with the DMAC component is an address definition (memory map) C header file. This can be used when the DMAC is programmed in a C environment. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 171: Register Access

    Note: Multi-block transfers—in which the source and destination are swapped during the transfer—are not supported. In a multi-block transfer, the direction must not change for the duration of the transfer. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 172: Fig 9-45 Multi-Block Transfer Using Linked Lists When Dmah_Chx_Stat_Src Set To True

    False. If this parameter is False, then the order of a Linked List item is as follows:  SARx  DARx  LLPx  CTLx  DSTATx User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 173: Fig 9-46 Multi-Block Transfer Using Linked Lists When Dmah_Chx_Stat_Src Set To False

    Table 9-19 row number, the LLI.SARx/LLI.DARx address may or may not be used to reprogram the DMAC SARx/DARx registers. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 174 This column assumes that the configuration parameter DMAH_CHx_CTL_WB_EN = True. If DMAH_CHx_CTL_WB_EN = False, then there is never writeback of the control and status registers regardless of transfer type, and all rows of this column are “No”. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 175 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 176: Programing Example

    `AHB_MASTER.write(0, (llp_addr + 12), ctlx[31:0], AhbWord32Attrb, handle[0]); `AHB_MASTER.write(0, (llp_addr + 16), ctlx[63:32], AhbWord32Attrb, handle[0]); // update pointers llp_addr = llp_addr + 20; // start of next LLI User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 177: Fig 9-49 Flowchart For Dma Programming Example

    Finally, enable the channel by writing a 1 to the ChEnReg.CH_EN bit; the transfer is performed. Fig 9-49 Flowchart for DMA programming example User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 178: Programming A Channel

    This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a 0 activates the hardware handshaking interface to handle source/destination requests. Writing a 1 activates the software handshaking interface to handle source and destination requests. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 179 DSTATARx register so that the destination status information can be fetched from the location pointed to by the User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 180 Table 9-19 (as discussed earlier). The DMAC then knows that the previously transferred block was the last block in the DMA transfer. The DMA transfer might look like that shown in Fig 9-50. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 181: Fig 9-50 Multi-Block With Linked Address For Source And Destination

    Fig 9-51 Multi-block with linked address for source and destination where SARx and DARx between successive blocks are contiguous The DMA transfer flow is shown in Fig 9-52. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 182: Fig 9-52 Dma Transfer Flow For Source And Destination Linked List Address

    Transfer width for the destination in the DST_TR_WIDTH field; Table 9-16 lists the decoding for this field.  Source master layer in the SMS field where the source resides. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 183: Fig 9-53 Multi-Block Dma Transfer With Source And Destination Address Auto-Reloaded

    The transfer is similar to that shown in Fig 9-53. Fig 9-53 Multi-block DMA transfer with source and destination address auto-reloaded User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 184: Fig 9-54 Dma Transfer Flow For Source And Destination Address Auto-Reloaded

    Write the channel configuration information into the CFGx register for channel x. Designate the handshaking interface type (hardware or software) for the source and destination peripherals; this is not required for memory. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 185 Table 9-19. If the DMAC is in Row 1 or Row 5, then the DMA transfer has completed. Hardware sets the transfer User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 186: Fig 9-55 Multi-Block Dma Transfer With Source Address Auto-Reloaded And Linked List Destination Address

    Fig 9-55 Multi-block DMA transfer with source address auto-reloaded and linked list destination address The DMA transfer flow is shown in Fig 9-56. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 187: Fig 9-56 Dma Transfer Flow For Source Address Auto-Reloaded And Linked List Destination Address

    Write the control information for the DMA transfer in the CTLx register for channel x. For example, in the register, you can program the following: User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 188 Row 1 of Table 9-19 before the last block of the DMA transfer has completed. The transfer is similar to that shown in Fig 9-57. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 189: Fig 9-57 Multi-Block Dma Transfer With Source Address Auto-Reloaded And Contiguous Destination Address

    Note: This type of multi-block transfer can only be enabled when either of the following parameters is set:  DMAH_CHx_MULTI_BLK_TYPE = 0  DMAH_CHx_MULTI_BLK_TYPE = LLP_CONT User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 190 DMAH_CHx_CTL_WB_EN = True, DMAH_CHx_STAT_DST = True, and CFGx.DS_UPD_EN is enabled. For conditions under which the destination status information is fetched from system memory, refer to the Write Back column of Table 9-19. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 191: Fig 9-59 Multi-Block Dma Transfer With Linked List Source Address And Contiguous Destination Address

    Fig 9-59 Multi-block DMA transfer with linked list source address and contiguous destination address The DMA transfer flow is shown in Fig 9-60. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 192: Disabling A Channel Prior To Transfer Completion

    If the DMAC is configured to use defined length bursts (DMAH_INCR_BURSTS = 0), disabling the channel via software prior to completing a transfer is not supported. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 193: Defined-Length Burst Support On Dmac

    INCR16 are required. The DMAC can be configured to use defined-length bursts by setting the configuration parameter DMAH_INCR_BURSTS to 0. In this mode, the DMAC will select the largest valid defined-length burst to complete the transfer. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 194: General Timers

    10.1.4 Functional Description 10.1.4.1 Upcounting Mode This timer is a 32-bit counter with its related auto-reload register. The counter can count up. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 195: Pulse Mode Timer

    One pulse mode PWM mode with polarity selection Statistic pulse width ● ● Statistic pulse number ● ● Interrupt generation ● ● User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 196: Block Diagram

    0, as well as the counter of the prescaler, but the prescale rate doesn’t change. In addition, if the URS bit in the TIMx_CR register is set, User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 197: Fig 10-3 Statistic Pulse Width Mode Diagram (Positive Edge Of Trgi Is Active For Capture)

    Fig 10-4 gives an example of statistic pulse number mode when prescaler division is 1, positive edge of TRGI is active for capture, and the ARR field equals to E6. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 198: Pwm Mode Timer

    Input pin 2 input capture 2 input capture Output pin 18 PWM out 6 PWM out Sleep mode ● 0%/100% ● ● User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 199: Block Diagram

    The counter, also the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes:  Counter register (TIMx_CNT)  Prescaler register (TIMx_PSC)  Auto-reload register (TIMx_ARR) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 200 Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Fig 10-6 Counter timing diagram with prescaler division change from 1 to 2 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 201 Fig 10-8 to Fig 10-13 show some examples of the counter behavior for different clock frequencies when the ARR field equals to 0x36. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 202: Fig 10-8 Counter Timing Diagram (Internal Clock Divided By 1)

    0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) Fig 10-10 Counter timing diagram (internal clock divided by 4) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 203: Fig 10-11 Counter Timing Diagram (Internal Clock Divided By N)

    (UIF) Auto-reload register Write a new value in TIMx_ARR Fig 10-12 Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 204: Fig 10-13 Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)

    The timer is only able to generate PWM in edge-aligned mode. Fig 10-14 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 205: Fig 10-14 Edge-Aligned Pwm Waveforms (Arr=8, Ccxp=0)

    Note: Since the 18 channels are independent with each other, when TRGI is used to trigger one channel to output PWM signal, it can also be used as capture source in input capture mode of another channel. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 206: Registers

    1: Counter is working. 15:9 RSVD Reserved CNT_RUN Counter run status  0: Counter is disabled.  1: Counter is enabled. RSVD Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 207 Access Reset Description 31:1 RSVD Reserved Update interrupt enable  0: Update interrupt is disabled.  1: Update interrupt is enabled. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 208 Counter value 10.4.1.7 TIMx Auto-reload Register (TIMx_ARR)  Name: TIMx auto-reload register (x = {0, 1, 2, 3})  Address offset: 0x1C User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 209: Tim4 Registers

    Counter run status  0: Counter is disabled  1: Counter is enabled RSVD Reserved CNT_STOP Counter stop  0: No action. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 210  1: CC0 interrupt is enabled. Update interrupt enable  0: Update interrupt is disabled.  1: Update interrupt is enabled. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 211 10.4.2.6 TIMx Counter Register (TIMx_CNT)  Name: TIM4 counter register  Address offset: 0x14  Reset value: 0x00000000  Read/write access: read/write User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 212 ARPE bit in the TIMx_CR register. 10.4.2.9 TIMx Capture/Compare Register 0 (TIMx_CCR0)  Name: TIM4 capture/compare register 0  Address offset: 0x20 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 213: Tim5 Registers

    TIM5 capture/compare register 7 TIMx_CCR8 0x40 TIM5 capture/compare register 8 TIMx_CCR9 0x44 TIM5 capture/compare register 9 TIMx_CCR10 0x48 TIM5 capture/compare register 10 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 214  Reset value: 0x00000000  Read/write access: read/write … ARPE UDIS RSVD RSVD RSVD Name Access Reset Description 31:9 RSVD Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 215 1: CC13 interrupt is enabled CC12IE Capture/compare 12 interrupt enable  0: CC12 interrupt is disabled  1: CC12 interrupt is enabled User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 216 CC5IF CC4IF CC3IF CC2IF CC1IF R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1 R/W1C User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 217 Access Reset Description 31:19 RSVD Reserved CC17G Refer to CC0G description CC16G Refer to CC0G description CC15G Refer to CC0G description User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 218 10.4.3.7 TIMx Prescaler Register (TIMx_PSC)  Name: TIM5 prescaler register  Address offset: 0x18  Reset value: 0x00000000  Read/write access: read/write … … User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 219 CC0 channel configured as input  0: Positive edge of TRGI is active for capture.  1: Negative edge of TRGI is active for capture. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 220 Name: TIM5 capture/compare register 2  Address offset: 0x28  Reset value: 0x00000000  Read/write access: read/write CC2M CC2P OC2PE CC2E RSVD RSVD CCR2 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 221 Refer to OC0PE description in TIMx_CCR0 CC4E Refer to CC0E description in TIMx_CCR0 23:16 RSVD Reserved 15:0 CCR4 Refer to CCR0 description in TIMx_CCR0 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 222 Name: TIM5 capture/compare register 7  Address offset: 0x3C  Reset value: 0x00000000  Read/write access: read/write RSVD CC7M CC7P OC7PE CC7E RSVD User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 223 Name Access Reset Description 31:28 RSVD Reserved CC9M Refer to CC0M description in TIMx_CCR0 CC9P Refer to CC0P description in TIMx_CCR0 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 224 Refer to CCR0 description in TIMx_CCR0 10.4.3.21 TIMx Capture/Compare Register 12 (TIMx_CCR12)  Name: TIM5 capture/compare register 12  Address offset: 0x50 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 225 Name: TIM5 capture/compare register 14  Address offset: 0x58  Reset value: 0x00000000  Read/write access: read/write CC14M CC14P OC14PE CC14E RSVD RSVD CCR14 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 226 Refer to OC0PE description in TIMx_CCR0 CC16E Refer to CC0E description in TIMx_CCR0 23:16 RSVD Reserved 15:0 CCR16 Refer to CCR0 description in TIMx_CCR0 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 227: Design Implementation

    TIM4 TIM0/1/2/3 timer_pwm_ch18 TIM5 Fig 10-16 Block diagram User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 228: Synchronous Data From Fast Clock To Slow Clock

    Check whether the timer is running Poll CNT_RUN in TIMx_EN Optional Change ARR on the fly Configure TIMx_ARR Recommend to set ARPE bit in TIMx_CR User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 229: Pulse Mode

    10.6.3 PWM Mode PWM mode: support TIM5. 10.6.3.1 Repeated Mode The PWM repeated mode configuration flow is illustrated in Table 10-11. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 230: Input Capture Mode

    In input capture mode, different channels can be used to capture the double edge of TRGI, thus to get the width of TRGI. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 231: Real-Time Clock (Rtc)

    The RTC is connected under APB buses. The total block diagram is shown in Fig 11-1. APB Bus rtc_apbslv_wrapper rtc_reg rtc_clk_rst_gen rtc_ctrl rtc_alarm rtc_clk_div_spre rtc_clk_div_apre rtc_counter Fig 11-1 RTC block diagram User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 232: Rtc Clock Select Diagram

    A 9-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register.  A 9-bit synchronous prescaler configured through the PREDIV_S bits of the RTC_PRER register. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 233: Auto-Trigger Calibration Circuit

    ACAL_SEL[1:0] = 11 and the ACAL_THES[5:0] is set, the ACAL_CNT[5:0] updates once per day. ACAL_SEL[1:0] Minute_udp Hour_udp ACAL_CNT[5:0] Day_udp xtal_req_32k ACAL_THES[5:0] Fig 11-5 xtal_req_32k block diagram User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 234: Programmable Alarm

    If RECALPF is set to 0, write a new value to RTC_CALIBR if necessary, RECALPF is then automatically set to 1. Within three clk_apre cycles after the write operation to RTC_CALIBR, the new calibration settings take effect. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 235: Day Threshold Program

    Second tens in BCD format SU[3:0] Second units in BCD format 11.3.2 RTC Control Register (RTC_CR)  Name: RTC control register User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 236 1: Adds 1 hour to the current time. This can be used for summer time change. This bit is always read as 0. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 237: Rtc Initialization And Status Register (Rtc_Isr)

    It is cleared by hardware when ALME bit has been set to 1 in RTC_CR register.  0: Alarm update isn’t allowed  1: Alarm update is allowed User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 238: Rtc Prescaler Register (Rtc_Prer)

    0: Positive calibration: time update frequency is increased  1: Negative calibration: time update frequency is decreased 13:7 RSVD Reserved Digital calibration User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 239: Rtc Alarm 1 Register Low (Rtc_Almr1L)

    This register is write protected, and can be written only when ALMWF is set to 1 in RTC_ISR register, or in initialization mode. RSVD MSK3 DAY[8:0] RSVD Name Access Reset Description 31:10 RSVD Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 240: Rtc Write Protection Register (Rtc_Wpr)

    01: 32K auto calibration once every ACAL_THRES[5:0] minutes  10: 32K auto calibration once every ACAL_THRES[5:0] hours  11: 32K auto calibration once every ACAL_THRES[5:0] days User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 241: Operation Flow

    The calibration configure flow is shown in Table 11-5. Table 11-5 Calibration configure flow Step What to do How to do Comments User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 242: Daylight Saving Time

    It is early enough that the entire continental U.S. switches by daybreak, and the changeover occurs before most early shift workers and early churchgoers are affected. (http://www.webexhibits.org/daylightsaving/b.html) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 243: Watchdog Timer (Wdt)

     5: 0x03F  6: 0x07F  7: 0x0FF  8: 0x1FF  9: 0x3FF  10: 0x7FF  11~15: 0xFFF User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 244 Watchdog timer counts with 32.768kHz/(DivFactor + 1), the minimum dividing factor is 1. The formula of dividing factor computation is: DivFactor = (u16) (Timeout * 100)/(Count * 3) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 245: Inter-Integrated Circuit (I C) Interface

    C bus, which is 100K/s in Standard Mode, 400K/s in Fast Mode and 3.4M/s in High Speed Mode (not supported in Ameba-D). User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 246: I 2 C Terminology

    Multi-master – the ability for more than one master to co-exist on the bus at the same time without collision or data loss.  Arbitration – the predefined procedure that authorizes only one master at a time to take control of the bus. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 247: I 2 C Behavior

    (NACK) the transaction after the last byte is received, and then the master issues a STOP condition or addresses another slave after issuing a RESTART condition. This behavior is illustrated in Fig 9-9. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 248: I 2 C Protocols

    SDA line while SCL is 1. Fig 9-10 shows the timing of the START and STOP conditions. When data is being transmitted on the bus, the SDA line must be stable when SCL is 1. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 249: Fig 13-5 7-Bit Address Format

    C places the data in the receive buffer and issues a General Call interrupt. 0000 000 START byte. 0000 001 CBUS address. I C ignores these accesses. 0000 010 Reserved 0000 011 Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 250: Fig 13-7 Master-Transmitter Protocol

    START condition except it occurs after the ACK pulse. Operating in master mode, the I C can then communicate with the same slave using a transfer of a different direction. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 251: Fig 13-8 Master-Receiver Protocol

    C acts as a slave, set IC_ACK_GENERAL_CALL (0x98) bit 0 to 1 to respond with a ACK when it receives a General Call, and a General Call interrupt will be issued. When set this bit to 0, the I C does not generate General Call interrupts. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 252: Tx Fifo Management And Start, Stop And Restart Generation

    C when the Tx FIFO becomes empty while operating as a master receiver, as well as showing the generation of a STOP condition. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 253: Fig 13-14 Master Receiver - Tx Fifo Empties/Stop Generation

    STOP condition. START condition. Fig 13-17 Master transmitter — Stop bit of IC_DATA_CMD set/Tx FIFO not empty User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 254: Multiple Master Arbitration

    Control of the bus is determined by address or master code and data sent by competing masters, so there is no central master nor any order of priority on the bus. Slaves are not involved in the arbitration process. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 255: Clock Synchronization

    C asserts the RD_REQ interrupt (bit 5 of the IC_RAW_INTR_STAT register) and holds the SCL line low. It is in a wait state until software responds. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 256 Tx FIFO could be written with n number bytes and the remote master receives it as a continuous stream of data. For User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 257: Ic_Clk Frequency Configuration

    C bus transaction can take place in order to ensure proper I/O timing. The *CNT registers are:  IC_SS_SCL_HCNT  IC_SS_SCL_LCNT  IC_FS_SCL_HCNT  IC_FS_SCL_LCNT  IC_HS_SCL_HCNT  IC_HS_SCL_LCNT User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 258 Standard Speed Mode (100K): 40∗10000  IC_SS_SCL_HCNT = = 45 ( 40+47 ) ∗100 47∗10000  IC_SS_SCL_LCNT = = 54 ( 40+47 ) ∗100 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 259: Programmable Sda Hold Time

    For optimal operation, DMA.CTLx.DEST_MSIZE should be set at the FIFO level that triggers a transmit DMA request; that is: User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 260: Low Power Mode

    Slave device can sleep and be wakeup when the address sent by master matching its address. Ameba-D I C also supports low power mode to reduce power consumption. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 261: Registers

    C SDA Setup Register IC_ACK_GENERAL_CALL 0x98 C ACK General Call Register IC_ENABLE_STATUS 0x9C C Enable Status Register IC_DMA_CMD 0xA0 C DMA Command Register User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 262: Registers And Field Descriptions

    C transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. RSVD Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 263 Note: It is not necessary to perform any write to this register if I C is enabled as an I C slave only. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 264 C to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the I C will stop acknowledging. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 265 C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 266 C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 267 The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. RSVD RSVD R_DMA_I2C_DONE R_MS_CODE_DET RSVD R_ADDR_MATCH R_GEN_CALL R_START_DET R_STOP_DET R_ACTIVITY User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 268 Reserved M_DMA_I2C_DONE These bits mask their corresponding interrupt status bits in the IC_INTR_STAT register. M_MS_CODE_DET RSVD M_ADDR_MATCH M_GEN_CALL M_START_DET M_STOP_DET M_ACTIVITY User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 269 C is acting as a slave-transmitter, this bit is set to 1 if the master does not RX_DONE acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 270 A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 271 Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. 13.3.2.19 IC_CLR_RX_OVER  Name: Clear RX_OVER Interrupt Register  Size: 32 bits User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 272 RSVD Reserved CLR_TX_ABRT Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 273 Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. 13.3.2.26 IC_CLR_START_DET  Name: Clear START_DET Interrupt Register  Size: 32 bits User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 274 C goes into IDLE state. 13.3.2.29 IC_STATUS  Name: I C Status Register  Size: 32 bits  Address offset: 0x70  Read/write access: read-only User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 275 The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. … User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 276 13.3.2.33 IC_TX_ABRT_SOURCE  Name: I C Transmit Abort Source Register  Size: 32 bits  Address offset: 0x80  Read/write access: read-only User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 277 13.3.2.34 IC_SLV_DATA_NACK_ONLY  Name: Generate Slave Data NACK Register  Size: 32 bits  Address offset: 0x84  Read/write access: read/write User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 278 Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 279 The register controls whether I C responds with a ACK or NACK when it receives an I C General Call address. … ACK_GEN_CALL RSVD User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 280 RSVD Reserved DMODE_RESTART This bit controls whether a RESTART is issued after the byte is sent or received in DMA mode. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 281 13.3.2.44 IC_SLEEP  Name: I C Sleep Mode Register  Size: 32 bits  Address offset: 0xAC  Read/write access: read/write … User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 282 Size: 32 bits  Address offset: 0xEC  Read/write access: read/write … IC_DIG_FLTR_SEL IC_DIG_FLTR_DEG RSVD RSVD Name Access Reset Description 31:9 RSVD Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 283 Size: 32 bits  Address offset: 0xFC  Read/write access: read-only … IC_COMP_VERSION Name Access Reset Description 31:0 IC_COMP_VERSION 0x20170627 C version number User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 284: Universal Asynchronous Receiver/Transmitter (Uart)

    XTAL clock, XTAL clock/20, OSC clock apb_slv_ wrap regmng Fig 14-1 UART block diagram User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 285: Register

    Baud Rate Monitor Control Register REG_MON_BAUD_STS 0x0048 Baud Rate Monitor Status Register REG_MON_CYC_NUM 0x004C Clock Cycle Monitored Register It displays the actually monitored clock cycle. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 286: Ier

    … INT_ID[2:0] INT_PEND RSVD Name Access Reset Description 31:4 RSVD Reserved  INT_ID[2:0] 3’b100 3’b011:  Interrupt Priority: 1st priority (int_3) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 287: Lcr

    Note:  DLL/DLM only can be access when DLAB = 1.  IER only can be access when DLAB = 0. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 288: Mcr

    This bit controls the RTS_ output. Bit 1 affects the RTS_ output in a manner identical to that described below for bit 0. Data Terminal Ready (DTR) signal control User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 289: Lsr

    14.2.6 MSR  Name: Modem Status Register  Size: 32 bits  Address offset: 0x0018  Read/write access: read-only … RSVD User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 290: Scr

    Rx break signal interrupt status, Write 1 to clear. SCRATCH[6] Rx break signal interrupt enable RSVD Reserved PIN_LB_TEST For UART IP txd/rxd/rts/cts pin loopback test RSVD Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 291: Stsr

    Size: 32 bits  Address offset: 0x0024  Read/write access: write-only … RSVD TXDATABIT7 TXDATABIT6 TXDATABIT5 TXDATABIT4 TXDATABIT3 TXDATABIT2 TXDATABIT1 TXDATABIT0 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 292: Miscr

     IRDA_ENABLE 1: UART co-works with IrDA SIR mode, which means that txd/rxd are IrDA signals.  0: UART mode only. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 293: Irda_Sir_Tx_Pw_Ctrl

    Function enable of SIR Rx filter. 14.2.14 BAUD_MON  Name: Baud Rate Monitor Register  Size: 32 bits  Address offset: 0x0034  Read/write access: read/write User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 294: Dbg_Uart

    RXBAUD_ADJ[10:0] One factor of baud rate calculation for Rx path, similar with XFACTOR_ADJ[10:0]. R_RST_NEWRX_N Reset Rx path, low active RSVD Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 295: Reg_Mon_Baud_Ctrl

    14.2.19 REG_MON_CYC_NUM  Name: Clock Cycle Monitored Register  Size: 32 bits  Address offset: 0x004C  Read/write access: read-only … User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 296: Reg_Rx_Byte_Cnt

    Writing 1 to this bit is self-clearing. CLEAR_RXFIFO Writing logic ‘1’ to this bit clears the Receiver FIFO and resets its logic. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 297: Design Implementation

    Real Baud Rate Error Rate (%) 40MHz XTAL 1200 1200 2400 2400 4800 4800 The calculation of error rate retains four decimal places. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 298: Clock Structure Of Rx Path

    4800_0214[26] XTAL 40MHz XTAL 2MHz log uart rx clk OSC 2MHz Fig 14-2 Clock structure of KM0 log UART Rx path User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 299: Irda_Sir_Encoder/Decoder

    Fig 14-5 gives the relationship between IrDA signal and UART signal. Pulse width of IrDA signal is 3-bit or 16-bit width of UART signal. Parameter ovsr[19:0] shall be multiple of 16 when IrDA mode is used. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 300: Auto-Flow Control

    FIFO or read from it for the last 4 characters times 3’b001 Tx FIFO empty Tx FIFO empty Write to the Tx FIFO or read the IIR User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 301: Dma Flow Control

    GDMA, on the same time, UART sets DUMMY_FLAG in the MISCR register for software judgement. timeout rx_dma_req rx_dma_single rx_dma_last rx_dma_ack Fig 14-8 DMA interface timing diagram User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 302: Infrared Radiation (Ir)

    Tx module modulates and transmits those IR signals. IR Tx flow is shown in Fig 15-2 IR Tx flow. Carrier Space symbol Waveform Carrier Carrier No carrier No carrier Carrier Fig 15-2 IR Tx flow User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 303: Features

    SCLK (100MHz) IR_TX Scaler Carrier Generator Modulation FIFO Interrupt Interrupt Control Sampling IR_RX Register Glitch Filter Fig 15-4 IR block diagram User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 304: Scaler

    IR Rx count threshold configure register IR_RX_FIFO 0x0028 IR Rx FIFO register IR version register IR_VERSION 0x002C IR IP version register User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 305: Ir Clock Control Register

    0: Tx mode  1: Rx mode  IR_TX_START 0: FSM stops at idle state.  1: FSM runs. 29:28 RSVD Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 306  1: Empty  IR_TX_FIFO_FULL 0: Not full  1: Full 13:8 IR_TX_FIFO_OFFSET Tx FIFO offset is from 0 to 32. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 307 Tx FIFO empty interrupt Write 1 to clear IR_TX_FIFO_CLR Write 1 to clear Tx FIFO 15.3.2.5 IR_TX_FIFO  Name: IR Tx FIFO register User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 308: Ir Rx Registers

    IR_RX_TRIGGER_MODE 00: High -> low trigger  01: Low -> high trigger  10: High -> low or low ->high trigger User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 309 1: Enable IR_RX_FIFO_FULL_INT_EN Rx FIFO full interrupt  0: Disable  1: Enable 15.3.3.2 IR_RX_SR  Name: IR clock division register User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 310  Name: IR clock division register  Size: 32 bits  Address offset: 0x0020  Read/write access: write … IR_RX_FIFO_CLR RSVD User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 311 Note: User can’t read this register under Tx mode. … IR_RX_LEVEL IR_RX_CNT Name Access Reset Description IR_RX_LEVEL Rx Level  1: High level  0: Low level User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 312: Ir Version Register

    Write data to Tx FIFO. Start transfer by writing 1 to IR_TX_START. (10) Write more data to Tx FIFO if needed (based on TX_FIFO_LEVEL_INT). User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 313: Receiver Application

    For receiver application, initialization process is the same as IR learning. It is important to note that diode input increases CPU load, because software must de-module carrier signal. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 314: Key-Scan

    Fig 16-1 Key-Scan block diagram The typical application setup is shown in Fig 16-2 (take 6*6 keypad array for example), external keypad is needed. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 315: Work Principle

    Interval time between each full scan is configurable. Once all keys are detected release, there is a release timer to confirm that, then an all release interrupt is triggered and state machine enters idle state. The Key-Scan timing is shown in Fig 16-4. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 316: Fig 16-3 Key-Scan Flow

    All Release Interrupt *Valid Key: Key Values of the First Scan and the Second Scan are identical Fig 16-3 Key-Scan flow User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 317: Fig 16-4 Key-Scan Timing

    Key release Key 1 Press Event Trigger Mode Regular Scan Mode Fig 16-5 Difference of FIFO items between two work modes User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 318: Fifo Mechanism

    The blue part works under bus clock domain (10M), it is gated in low power modes. In bus clock domain, some of the logic works in scan_clk frequency, which is divided from bus clock. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 319: Shadow Key Problem

    1 column is driven low at a time. While this is done to each column, the RTL8721D reads the row inputs, to determine which keys on a column are being pressed. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 320: Fig 16-8 4*3 Keypad Example

    Keypad matrices can support multiple key presses properly, if care is taken when choosing the layout. In Fig 16-10, you see a 3-button combination which works as expected. Fig 16-9 Shadow key condition User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 321: Registers

    Read/write access: read/write … … KS_CLK_DIV RSVD Name Access Reset Description 31:12 RSVD Reserved 11:0 KS_CLK_DIV scan_clk = bus clock/(KS_CLK_DIV +1) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 322: Ks_Tim_Cfg0

    = scan_clk * (KS_RELEASE_TIMER + 1) Release timer ranges from 100ns to 1.68s. 16.3.4 KS_CTRL  Name: Key-Scan Control Register User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 323: Ks_Fifo_Cfg

    Write 1 to clear FIFO data 16.3.6 KS_COL_CFG  Name: Key-Scan Column Configuration Register  Size: 32 bits  Address offset: 0x14 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 324: Ks_Row_Cfg

    … KS_FIFO_DATA_LEVEL RSVD Name Access Reset Description 31:18 RSVD Reserved KS_FIFO_FULL FIFO full status KS_FIFO_EMPTY FIFO empty status 15:5 RSVD Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 325: Ks_Data

    0x1: Unmask scan finish interrupt  KS_FIFO_NOTEMPTY_INT_MASK 0x0: Mask FIFO non-empty interrupt  0x1: Unmask FIFO non-empty interrupt  KS_ALL_RELEASE_INT_MASK 0x0: Mask all release interrupt User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 326: Ks_Icr

    Masked FIFO full interrupt status KS_SCAN_FINISH_INT_STATUS Masked scan finish interrupt status KS_FIFO_NOTEMPTY_INT_STATUS Masked FIFO nonempty interrupt status KS_ALL_RELEASE_INT_STATUS Masked all release interrupt status User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 327: Ks_Isr_Raw

    Name: Key-Scan Interval Polarity and Discharge Configuration Register  Size: 32 bits  Address offset: 0x34  Read/write access: read/write … User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 328 0x0: Disable the discharge of the column spurious capacitance. KS_INTERVAL_POLARITY Configure the column polarity in debounce and interval phase  0x1: Drive low  0x0: Open drain floating User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 329: Audio Codec (Ac)

    Digital Audio Codec (AC) @40MHz DAC-L HP driver Virtual GND Anti-Pop External HP driver DAC-R DSP/DAC Fig 17-1 Audio codec diagram User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 330: Key Features

    ASRC is required for ADC/DAC paths 24 bits information for ADC and DAC paths Sampling Frequency 8/16/32/44.1/48/88.2/96kHz  Over-Sampling Rate OSR = 128 * fs User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 331: Specifications

    0dBFS signal Load=10kΩ Signal to Noise Ratio =1kHz (SNR @single-end mode) B/W=20~20kHz AVCC=2.8V THD+N < 0.01% 0dBFS signal Load=10kΩ Digital Gain -65.625 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 332: Adc Path

    Microphone mode Input impedance kΩ Input impedance Input capacitance THD+N (microphone input) @30mV input 0.02 THD+N (line input) @-3dBFS 0.01 ADC channels User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 333: Application And Implementation

    In this mode, both N-end and P-end drive the available analog audio signal. Users should select the differential jack and earphone accordingly. The differential mode connection with a headphone jack is shown in Fig 17-3. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 334: Audio Input

    Fig 17-5 shows the situation of connecting the left channel of line-in signal to AUX_L, and connecting the right channel to AUX_R accordingly. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 335: Fig 17-5 Line-In Mode Connection

    Fig 17-8 and Fig 17-9 show the situation of connecting DMIC_CLK/DMIC_DATA with digital mic-phone, while MICBIAS provides the mic-phone power supply.  Tie the L/R of digital mic-phone to ground or VDD if only one digital mic-phone is placed. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 336: Fig 17-8 Digital Mic Mono Mode Connection

    Fig 17-10 shows the mono PDM format, and the stereo PDM format is shown in Fig 17-11. DAT A DAT A (R) DAT A (R) DAT A (R) Fig 17-10 Mono PDM format User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 337: Registers

     1’b0: Power down  1’b1: Power on [6:5] DPRAMP_CSEL 2'b00 Depop C size selection  2’b00: 1x  2’b01: 2x User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 338 1'b0 Headphone right channel enable amplifier control  1’b0: Disable  1’b1: Enable HPO_ENDPL 1'b0 Headphone left channel enable depop control User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 339 1'b1: Power on MICBIAS_ENCHX 1'b0 MICBIAS enable chopper clock  1’b0: Disable  1’b1: Enable [10] MICBIAS_POW 1'b0 MICBIAS power control User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 340  2’b11: 0.49*VDD [15:12] RSVD 2'b00 Reserved 17.6.1.5 0x04 Address Name Access Reset Description  0x04 [1:0] DEBUG_BUS_SEL 2'b00 2'b00: debug_bus_a User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 341: Digital Part

     5'h0d: -27.0dB  5'h0e: -25.5dB  5'h0f: -24.0dB  5'h10: -22.5dB  5'h11: -21.0dB  5'h12: -19.5dB  5'h13: -18.0dB User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 342 RSVD 3'h0 Reserved 17.6.2.4 0x11 Address Name Access Reset Description 0x11 ADC_L_DMIC_RI_FA_SEL 1'b0 DMIC Data Latching Control  1’b0: Rising latch User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 343 3'b010: fs = 48k or 44.1k corresponding fc = (30~2168Hz)/(28~1992Hz)  3'b011: fs = 96k or 88.2k corresponding fc = (30~2034Hz)/(28~1869Hz) [7:6] ADC_L_DMIC_BOOST_GAIN 2'b00 DMIC boost gain control User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 344 Reserved ADC_R_AD_LPF2ND_EN 1'b1 ADC SRC 2nd LPF control  1’b0: Disable  1’b1: Enable ADC_R_AD_LPF1ST_EN 1'b1 ADC SRC 1st LPF control User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 345 ADC zero detection time out select  2'b00: 1024*16 samples  2'b01: 1024*32 samples  2'b10: 1024*64 samples  2'b11: 64 samples [15:13] RSVD 3'b000 Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 346  4'h2: 192K  4'h3: 32K  4'h4: Reserved  4'h5: 16K  4'h6: Reserved  4'h7: 8K  4'h8: 44.1K User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 347 Set ADC filter right channel digital MIC path clock  1'b0: Turn off clock and reset  1'b1: Turn on clock [15] DMIC_CLK_EN 1'b1 Set digital MIC clock User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 348 Set asynchronous sample rate conversion  1'b0: Disable  1'b1: Enable [6:5] SIDETONE_IN_SEL 2'h0 sidetone input selection  2'b00: From adc_l_lpf User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 349 7'h5F ALC back boost gain control (0.375dB/step)  7'h00: -35.625dB  7'h01: -35.250dB   7'h5f: 0.000dB   7'h7f: 12.000dB User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 350  3'b001: +-0.375dB  3'b010: +-0.75dB  3'b011: +-1.125dB  3'b100: +-1.5dB  3'b101: +-1.875dB  3'b110: +-2.25dB  3'b111: +-2.625dB User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 351 [15:14] ALC_COMP_RATIO_SEL 2'b11 ALC DRC compression ratio select control  2'b00: 1:1  2'b01: 1:2  2'b10: 1:4  2'b11: 1:8 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 352 6'h3c: -45dB (-0.75dB/step) [12:8] ALC_THNOISE 5'h0 AGC noise gate threshold level (at amplitude domain) control  5'h00: -24.00dB  5'h01: -25.50dB User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 353 1'b1: alc_bypass function with cross detection [15] ALC_ATK_HOLD_EN 1'b0 enable control for attack hold function in ALC  1'b0: Attack hold function is disabled User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 354 1'b0: Recover mode  1'b1: Attack mode [11] ALC_OP_MODE_R 1’b0 Status of ALC operation mode in R channel  1'b0: Recover mode User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 355 0xF6 DAC_L_SILENCE_DET_ 1'b0 dac_l_silence data detection enable control  MONO_EN 1'b0: Disable dac_l_silence data detection  1'b1: Enable dac_l_silence data detection User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 356  O_DATA_BIT 2'b00: 16-bit, corresponding to dac_r_silence data threshold =-78db  2'b01: 20-bit, corresponding to dac_r_silence data threshold =-102db User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 357  O_DEBOUNCE_SEL 3'b000: Debounce 80ms at sample rate 48kHz  3'b001: Debounce 160ms at sample rate 48kHz User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 358  MONO_STATUS 1'b0: adc_r_silence detection is resting (clock is gating)  1'b1: adc_r_silence detection is working [15:12] RSVD 4’h0 Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 359 8'hAF: 0dB  8'h00: -65.625dB DAC_R_DAHPF_EN 1'b1 Mon DAC Rch Narrow-band 1st HPF enable control  1'b0: Disable  1'b1: Enable User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 360: Dac_Eq

    2'b11: {LSB+2, LSB+1, LSB} RSVD 1'b0 Reserved DAC_L_BQ_EQ_CD_FLAG 1'b0 DAC Lch Biquad filter cross detect status  1'b0: No data zero cross User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 361 Write "1" to send clear status pulse [15] DAC_L_BIQUAD_STATUS_1 1'b0 DAC Lch 1st-band Biquad filter status  1'b0: Normal  1'b1: Overflow User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 362 1'b1: Overflow 17.6.3.12 0x3F ~ 0x40 Address Name Access Reset Description 0x3F [15:0] DAC_L_BIQUAD_H0_3[15:0] 16'h0000 DAC Lch EQ 3rd-band coefficient h0 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 363 2's complement in 4.25 format, which means 0x4A [12:0] DAC_L_BIQUAD_H0_4[28:16] 13'h0200 that the range is from –8~7.99. [15:13] RSVD 3'b000 Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 364 3'b000 Reserved 17.6.3.23 0x55 ~ 0x56 Address Name Access Reset Description 0x55 [15:0] DAC_L_BIQUAD_B1_5[15:0] 16'h0 DAC Lch EQ 5th-band coefficient b1 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 365 2'b01: LSB  2'b10: {LSB+1, LSB}  2'b11: {LSB+2, LSB+1, LSB} RSVD 1'b0 Reserved DAC_R_BQ_EQ_CD_FLAG DAC Rch Biquad filter cross detect status User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 366 Write "1" to send clear status pulse [15] DAC_R_BIQUAD_STATUS_1 1'b0 DAC Rch 1st-band Biquad filter status  1'b0: Normal  1'b1: Overflow User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 367 1'b1: Overflow 17.6.3.38 0x72 ~ 0x73 Address Name Access Reset Description 0x72 [15:0] DAC_R_BIQUAD_H0_3[15:0] 16'h0000 DAC Rch EQ 3rd-band coefficient h0 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 368 2's complement in 4.25 format, which means 0x7D [12:0] DAC_R_BIQUAD_H0_4[28:16] 13'h0200 that the range is from –8~7.99. [15:13] RSVD 3'b000 Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 369 3'b000 Reserved 17.6.3.49 0x88 ~ 0x89 Address Name Access Reset Description 0x88 [15:0] DAC_R_BIQUAD_B1_5[15:0] 16'h0 DAC Rch EQ 5th-band coefficient b1 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 370: Adc_Eq

    1'b1: Enable (Normal mode) [3:2] ADC_L_BQ_EQ_DITHER_SEL 2'b00 ADC Lch EQ dither control  2'b00: Normal  2'b01: LSB  2'b10: {LSB+1, LSB} User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 371 1'b0: Normal  1'b1: Overflow Write "1" to send clear status pulse [15] ADC_L_BIQUAD_STATUS_1 1'b0 ADC Lch 1st-band Biquad filter status User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 372 Write "1" to send clear status pulse [15] ADC_L_BIQUAD_STATUS_2 1'b0 ADC Lch 2nd-band Biquad filter status  1'b0: Normal  1'b1: Overflow User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 373 1'b1: Overflow 17.6.4.17 0xAF ~ 0xB0 Address Name Access Reset Description 0xAF [15:0] ADC_L_BIQUAD_H0_4[15:0] 16'h0000 ADC Lch EQ 4th-band coefficient h0 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 374 2's complement in 4.25 format, which means 0xBA [12:0] ADC_L_BIQUAD_H0_5[28:16] 13'h0200 that the range is from –8~7.99. [15:13] RSVD 3'b000 Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 375  1'b0: Disable (Test mode)  1'b1: Enable (Normal mode) [3:2] ADC_R_BQ_EQ_DITHER_SEL 2'b00 ADC Rch EQ dither control  2'b00: Normal User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 376 1'b0: Disable  1'b1: Enable [14] ADC_R_BIQUAD_WCLR_1 1'b0 ADC Rch 1st-band Biquad filter write clear  1'b0: Normal  1'b1: Overflow User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 377 Write "1" to send clear status pulse [15] ADC_R_BIQUAD_STATUS_2 1'b0 ADC Rch 2nd-band Biquad filter status  1'b0: Normal  1'b1: Overflow User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 378 1'b1: Overflow 17.6.4.43 0xE2 ~ 0xE3 Address Name Access Reset Description 0xE2 [15:0] ADC_R_BIQUAD_H0_4[15:0] 16'h0000 ADC Rch EQ 4th-band coefficient h0 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 379 2's complement in 4.25 format, which means 0xED [12:0] ADC_R_BIQUAD_H0_5[28:16] 13'h0200 that the range is from –8~7.99. [15:13] RSVD 3'b000 Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 380 Write "1" to send clear status pulse [15] ADC_R_BIQUAD_STATUS_5 1'b0 ADC Rch 5th-band Biquad filter status  1'b0: Normal  1'b1: Overflow User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 381: Audio Codec Controller (Acc)

    Analog Core Fig 18-1 Ameba-D ACC + AC architecture 18.3.1 Block Diagram The ACC block diagram is shown in Fig 18-2. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 382: Data Part

    [7:0] [15:8] [7:0] Table 18-2 16-bit mono data without lr_swap/byte_swap Address Offset [31:24] [23:16] [15:8] [7:0] 0x0000 [15:8] [7:0] [15:8] [7:0] User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 383 0x000C [23:0] X @TX or 8’h0 @RX 0x0010 [23:0] X @TX or 8’h0 @RX 0x0014 [23:0] X @TX or 8’h0 @RX User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 384 8-bit mono data without lr_swap/byte_swap is listed in Table 18-13. Table 18-13 8-bit mono data without lr_swap/byte_swap Address Offset [31:24]: 0x11 [23:16]: 0x10 [15:8]: 0x01 [7:0]: 0x00 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 385: Fig 18-3 I S Audio Data Format

    S bus are shown in Fig 18-3 to Fig 18-8. Left Channel Right Channel SD_I 23 22 21 23 22 21 SD_O Fig 18-3 I S audio data format User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 386: Fig 18-4 Left-Justified Data Format

    Fig 18-6 PCM mode B-N data format Left Channel Right Channel SD_I 23 22 21 23 22 21 SD_O Fig 18-7 PCM mode A data format User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 387: Control Part

    SI write (slave side): 700 ns 100 ns SI_ENB 87.5ns 12.5ns 25ns 50ns SI_CK SI_DI SI_DO SI_D_OEN Fig 18-9 SI write timing User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 388: Acc Clock

    SPORT control 2 register SP_RX_DR 0x0010 SPORT Rx data register SP_FIFO_SR 0x0014 SPORT FIFO status register SP_ERROR_CNT_SR 0x0018 SPORT error counter register User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 389 1’b0: SPORT Rx is enabled  RX_LSB_FIRST 1’b0 1’b0: MSB first when Rx  1’b1: LSB first  TX_LSB_FIRST 1’b0 1’b0: MSB first when Tx User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 390 Address offset: 0x0008  Read/write access: read/write INT_ENABLE RX_SNK_LR_SW RX_SNK_BYTE_S TX_SRC_LR_S TX_SRC_BYTE_S MODE_128FS MODE_40MHZ RSVD CLEAR_RX_ER CLEAR_TX_ERR_ DEBUG_BUS_SEL R_CNT RSVD RSVD User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 391 18.4.1.5 SP_RX_DR  Name: SPORT Rx data register  Size: 32 bits  Address offset: 0x0010  Read/write access: read … SP_RX_DR User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 392 Note: This counter should always be zero if everything works well. TX_ERR_CNT 8’h0 Tx error counter (SPK path) Note: This counter should always be zero if everything works well. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 393: Control Registers

    3'h0 Reserved SI_WR_START 1'b0 1'b1: Start to perform SI write to audio codec This bit is cleared when SI_WRITE is done. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 394  1'b0: Turn off the clock. To save power, reset this bit to gate clock when the registers are already programmed. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 395: Serial Peripheral Interface (Spi)

    Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 396: Functional Description

    – output enable for the SPI master/slave  txd – transmit data line for the SPI master/slave  rxd – receive data line for the SPI master/slave User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 397: Fig 19-2 Spi Serial Format (Scph = 0)

    Fig 19-5 shows the timing diagram for the SPI format when the configuration parameter SCPH = 1. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 398: Fig 19-5 Spi Serial Format (Scph = 1)

    SCKDV is a bit field in the programmable register BAUDR, holding any even value in the range 0 to 65,534. If SCKDV is 0, then sclk_out is disabled. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 399 When set, data written from the APB is discarded. This interrupt remains set until you read the transmit FIFO overflow interrupt clear register (TXOICR). User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 400: Transfer Modes

    Fig 19-8 shows an example of the SPI configured as a serial master with all other devices on the serial bus configured as serial slaves. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 401: Fig 19-8 Spi Configured As Master Device

    Fig 19-9 illustrates this situation. Fig 19-9 Effects of round trip routing delays on sclk_out signal User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 402 Write the Transmit and Receive FIFO Threshold Level registers (TXFTLR and RXFTLR, respectively) to set FIFO threshold levels.  Write the IMR register to set up interrupt masks. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 403 Write TXFTLR and RXFTLR to set FIFO threshold levels.  Write the IMR register to set up interrupt masks. Enable the SPI slave by writing 1 to SSIENR. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 404: Dma Controller Interface

    The base address of SPI0 is 0x4007_8000, and the size is 2K; the base address of SPI1 is 0x4000_E000, and the size is 2K. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 405 Each of the 16-bit address locations are aliased to the DR; single accesses to the DR may use any of the 16-bit address locations. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 406: Registers And Field Descriptions

    0 – Slave txd is enabled 1 – Slave txd is disabled User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 407 12-bit serial data transfer 1100 13-bit serial data transfer 1101 14-bit serial data transfer 1110 15-bit serial data transfer 1111 16-bit serial data transfer User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 408 19.3.2.4 SER  Name: Slave Enable Register  Size: 1 bit  Address offset: 0x10  Read/Write access: read/write User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 409 This register controls the threshold value for the transmit FIFO memory. It is impossible to write to this register when the SPI is enabled. The SPI is enabled and disabled by writing to the SSIENR register. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 410 3 or more data entries are present in receive FIFO 0000_0011 ssi_rxf_intr is asserted when 4 or more data entries are present in receive FIFO … … User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 411 The status register may be read at any time. None of the bits in this register request an interrupt. RSVD DCOL RFNE TFNF BUSY RSVD Name Access Reset Description User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 412 SS_N Rising Edge Detect Interrupt Mask. This bit field is present only if the SPI is configured as a serial-slave device. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 413 Transmit FIFO Under Flow Interrupt Status. This bit field is present only if the SPI is configured as a serial-slave device. 0 – ssi_txu_intr interrupt is not active after masking User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 414 1 – ssi_mst_intr interrupt is active prior to masking When SPI is configured as serial-slave, this bit field is present as Frame Alignment Error Raw Interrupt Status. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 415 19.3.2.16 RXUICR  Name: Receive FIFO Underflow Interrupt Clear Register  Size: 1 bit  Address offset: 0x40  Read/write access: read User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 416 Writing to this register has no effect. 19.3.2.19 DMACR  Name: DMA Control Register  Size: 2 bits  Address offset: 0x4C  Read/write access: read/write User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 417 Address offset: 0x54  Read/write access: read/write This register is only valid when SPI is configured with a set of DMA interface signals. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 418 Read/write access: read This register is present only if SPI is configured as serial-slave. … SSRICR RSVD Name Access Reset Description User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 419 Note: If this register is programmed with a value that exceeds the depth of the internal shift registers (SSI_RX_DLY_SR_DEPTH), a zero (0) delay will be applied to the rxd sample. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 420 Size: 32 bits  Address offset: 0xFC  Read/write access: N/A This register is reserved for future use. Name Access Reset Description 31:0 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 421: Liquid Crystal Display Controller (Lcdc)

    Fig 20-1 shows the components of LCM with GRAM. In this application scenario, frame buffer is optional. Ameba-D Display Control LCDC Display Glass I8080 Control & DATA GRAM Frame Buffer (optional) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 422: Architecture

    LED_OE SYS_CLK INT/Status TE / VSYNC AXI_CLK APB_CLK SYS_CLK: 100MHz Data AXI_CLK: 100MHz Signal APB_CLK: 100MHz Fig 20-3 LCDC block diagram User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 423: Fig 20-4 Two Data Paths

    When I/O Tx FIFO is full, I/O write action halts. When Tx FIFO isn`t full, write ready signal is given by hardware and then software can write another pixel data. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 424: Mcu Interface

    Write cycle includes command setting and data writing. The timing parameters of command setting and data writing are illustrated in Fig 20-8 and Fig 20-9. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 425: Fig 20-8 Mcu I/F Command Setting Timing Parameters

    LCDC VSYNC interface starts synchronization to display the moving picture with MCU system interface according to the frame-synchronizing signal VSYNC. In this mode, LCDC controls the synchronization of frame. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 426: Fig 20-11 Mcu Vsync Mode Timing

    Table 20-1 MCU interface type I/F Type Data Format Support I80 8-bit RGB565 I80 9-bit RGB666 I80 16-bit RGB565 I80 18-bit RGB888 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 427: Rgb Interface

    … P1R4 : Pixel1/Red_bit4 Fig 20-15 8080 I/F 16-bit output 20.2.3 RGB Interface The RGB interface is shown in Fig 20-16. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 428: Fig 20-16 Rgb Interface

    Fig 20-17 RGB timing 20.2.3.2 DE Mode Driver determined valid data by ENABLE signal. The RGB DE mode timing is shown in Fig 20-18. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 429: Fig 20-18 Rgb De Mode Timing

    P1R1 P1G2 P1B1 P2R1 P2G2 … P1R0 P1G1 P1B0 P2R0 P2G1 … P1G0 P2G0 … P1R4 : Pixel1/Red_bit4 Fig 20-19 RGB I/F 6-bit output User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 430: Led Control

    20.2.4.1 LED Module The interface of LED module is shown in Fig 20-21. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 431: Fig 20-21 Led Interface

    Q5 Q6 16x8 LED 16x8 LED 16x8 LED Fig 20-21 LED interface The LED control timing is shown in Fig 20-22. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 432: Fig 20-22 Led Control Timing

    Frame Switching Timing Fig 20-22 LED control timing 20.2.4.2 LED Control Diagram The LED control diagram is shown in Fig 20-23. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 433: Fig 20-24 Led Color Mapping: Single Color And Single Channel

    20.2.4.3.2 Single Color and Two Channels The single color and two channels of LED color mapping is shown in Fig 20-25. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 434: Fig 20-25 Led Color Capping: Single Color And Two Channels

    20.2.4.3.4 Two Colors and Two Channels The two colors and two channels of LED color mapping is shown in Fig 20-27. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 435: Fig 20-27 Led Color Mapping: Two Colors And Two Channels

    20.2.4.3.6 Three Colors and Two Channels The three colors and two channels of LED color mapping is shown in Fig 20-29. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 436: Pinmux

    Parameters for maximum image size calculation：  Max. dot clock: MAX_DOT_CLK = system_clock/4 = 100MHz/4 = 25MHz  Refresh frequency: F = 60 (F/S) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 437 25MHz dot clock Mode Max. Support Resolution Common Support Resolution Refresh Frequency One channel mode 500*500 32*1024, 64*1024, 32*2048, etc. 60Hz User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 438: Registers

    LCDC_LED_TIMING 0x0084 LED control timings LCDC_LED_IDLE 0x0088 LED line and frame idle timings Image Control Registers LCDC_IMG_BASE_ADDR 0x0090 Image base address User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 439: Global Control Registers

    Read/write access: read/write IMAGEHEIGHT RSVD IMAGEWIDTH RSVD Name Access Reset Description 31:28 RSVD Reserved 27:16 IMAGEHEIGHT 0x140 The height of image (Y-channel based) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 440 Access Reset Description 31:8 DMAINTV The interval cycle count between two DMA requests. (for debug) Unit: bus clock cycle. RSVD Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 441: Interrupt And Status Registers

     Address offset: 0x0020  Read/write access: read/write … RSVD FRM_START_INT IO_TIMEOUT_INTEN LCD_LIN_INTEN LCDFRDINTEN DMAUNINTEN RSVD RSVD Name Access Reset Description User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 442 DMA FIFO underflow interrupt status. Write 1 to clear it.  0: No DMA FIFO underflow interrupt generated  1: Interrupt generated when DMA FIFO underflow happens User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 443 LINE_INT_POS RSVD Name Access Reset Description 31:12 RSVD Reserved 11:0 LINE_INT_POS Line Interrupt Position These bits configure the line interrupt position. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 444: Rgb Control Registers

    Read/write access: read/write RGB_SYNC_MODE RGBIFUPDATE DATPL ENPL HSPL VSPL DCLKPL RSVD RSVD R/W1S RSVD Name Access Reset Description 31:27 RSVD Reserved User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 445 Vertical synchronization signal width -1. Unit: inactive lines 20.3.3.3 LCDC_RGB_HSYNC_CFG  Name: LCDC RGB horizontal synchronization register  Size: 32 bits User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 446: Mcu Control Registers

    10: ACTIVE  11: VBP 20.3.4 MCU Control Registers 20.3.4.1 LCDC_MCU_CFG  Name: LCDC MCU configuration register  Size: 32 bits User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 447 The WR pulse polarity.  0: Data fetched at rising edge  1: Data fetched at falling edge RSPL The RS pulse polarity. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 448 The frequency of write clock is derived from the following equation: Write clock = SYS_CLK/(WRPULW + 2) where WRPULW is any even value between 0 and 1022. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 449: Led Control Registers

    20.3.5 LED Control Registers 20.3.5.1 LCDC_LED_CFG  Name: LCDC LED configuration register  Size: 32 bits  Address offset: 0x0080  Read/write access: read/write User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 450 31:24 RSVD Reserved 23:8 OEACTW OE Active Width Time – 1 (unit: dotclock). LATW LAT Width Time - 1 (unit: dotclock). User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 451: Image Control Registers

    Configure LCD via SPI if necessary. (Synchronous related parameters: HBP/HFP/HSW/VBP/VFP/VSW) Set LCDC_PLANE_SIZE register. Set LCDC_CTRL register as RGB interface. Set LCDC_DMA_MODE_CFG register as DMA Auto-mode. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 452: Mcu Dma Trigger-Mode

    Start transfer by writing 1 to the LCDCEN bit of LCDC_CTRL register. Send CMD & CMD parameters to LCD through LCDC_MCU_IO_DATA register. Write/read point to/from GRAM through I/O mode. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 453: Quadrature Decoder (Q-Decoder)

    IDX signal is located at state “00” in the example shown in Fig 21-2. Ameba-D Device Q-decoder Fig 21-1 Q-Decoder application scenario User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 454: Architecture

    V-Counter V-Counter Capture V-Low Limit Capture Event vccap_int_en V-Reload V-Timer eterr_int_en Velocity Measurement Unit SYS_CLK: 2MHz Fig 21-3 Q-Decoder block diagram User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 455: Position Measurement

    If CNT_SC = 1, only PHA changes can trigger position counter change. Direction 199 198 197 MPC=199 Fig 21-5 Position count state when CNT_SC = 0 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 456: Fig 21-7 Position Counter Reset On Index Pulse (Forward Direction)

    In the example of Fig 21-9, position counter resets on state (1, 0). In this case, position counter can also configured to be reset on state (1, 1), (0, 1), but state (0, 0) fails. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 457 When the default phase is high, the index pulse detection is the falling edge in the positive direction. The index pulse detection is the rising edge in the negative direction. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 458 Fig 21-11 Auto-index mechanism when IDX_INV = 0 Direction 199 198 197 Index pulse detection Fig 21-12 Auto-index mechanism when IDX_INV = 1 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 459: Velocity Measurement

    The position difference can be obtained from the velocity counter or subtract two position counter capture values. V ≒ △X / T ≒ V-counter / V- Reload ≒ [P-counter capture(t) - P-counter capture(t-1)] / V- Reload User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 460: Registers

    Name: Clock Configuration Register  Size: 32 bits  Address offset: 0x0000  Read/write access: read/write … SMP_DIV DBN_TM RSVD RSVD User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 461 1: Writing 1 to this bit resets the state machine and resets all functions. The Q-decoder reset can only be performed when the Q-decoder is disabled. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 462 Input signal (PHA, PHB & IDX) debouncing enable control  1: Enable debounce  0: Disable debounce 11:5 RSVD Reserved PCHG_LV Position changed interrupt trigger level User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 463: Position Measurement Registers

    Name: Q-Decoder Max Rotation Compare Register  Size: 32 bits  Address offset: 0x000C  Read/write access: read/write … … RSVD Name Access Default Description User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 464 21.3.2.4 REG_ISC  Name: Q-Decoder Index Signal Configuration Register  Size: 32 bits  Address offset: 0x0014  Read/write access: read/write … User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 465: Velocity Measurement Registers

     Address offset: 0x0018  Read/write access: read/write RSVD VT_DIV VMUC_MODE RSVD RSVD VUPLMT_INT_EN VLOWLMT_INT_EN VCCAP_INT_EN VMUC_RST VMUC_EN RSVD RSVD RSVD User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 466 Access Default Description 31:16 RSVD Reserved The velocity accumulation counter 15:0 Step is +1, -1 or to be reset to 0. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 467 21.3.3.5 REG_VTRLD  Name: Q-Decoder Velocity Time Reload Register  Size: 32 bits  Address offset: 0x0028  Read/write access: read/write User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 468: Interrupt Registers

    21.3.4 Interrupt Registers 21.3.4.1 REG_IMR  Name: Q-Decoder Interrupt Mask Register  Size: 32 bits  Address offset: 0x003C  Read/write access: read/write User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 469  1: Mask This interrupt is asserted when the rotation counter underflow occurs(0  0xFFF). ROF_INT_M Rotation counter overflow interrupt mask User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 470 0: No interrupt RC_INT_S R/WC  1: Interrupt pending  Reserved RSVD  0: No interrupt VUPLMT_INT_S R/WC  1: Interrupt pending User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 471 Position counter changed interrupt status  0: No interrupt  1: Interrupt pending Writing 1 to this bit clears this interrupt status. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 472: Inter-Ic Sound (I 2 S)

    Fig 1-2 shows I S 5.1 channel audio-out interface configuration. I2S out control DAC/ADC SD_o SD_i Fig 22-1 I S mono/stereo audio-out interface configuration User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 473: Functional Description

    In mono mode, WS changes as in stereo mode, but the difference is that there are no data transmitted when WS=1 (the right channel).  Frequency of WS equals to the sample rate. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 474: Operation Mode

    In this operation mode, as the master, the controller generates the SCK and WS signal; while the transmitter and the receiver act as the slave, the transmitter has to generate data under the control of external clocks. See Fig 22-6. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 475: Serial Data Standard

    For stereo, the left channel is transmitted when WS=1 and the right channel is transmitted when WS=0.  The transmitter and the receiver must have the same word length. This standard is rarely used. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 476: Clock Type

     If sample bit is 16-bit, MCK=8SCK=256WS  If sample bit is 24-bit, MCK=4SCK=256WS  If sample bit is 32-bit, MCK=4SCK=256WS User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 477: Fig 22-10 I 2 S Clock Tree

    7.5264MHz 22.05kHz 22.05kHz 0.7056MHz 1.4112MHz 5.6448MHz 14.7kHz 14.7kHz 0.4704MHz 0.9408MHz 3.7632MHz 11.025kHz 11.025kHz 0.3528MHz 0.7056MHz 2.8224MHz 7.35kHz 7.35kHz 0.2352MHz 0.4704MHz 1.8816MHz User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 478: Memory Block

    When the sample bit is 16-bit or 32-bit, the FIFO allocation of the mono channel are illustrated in Fig 22-12 and Fig 22-13. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 479: Fig 22-12 Fifo Allocation Of Mono Channel (Sample Bit = 16-Bit)

    When the sample bit is 16-bit or 24-bit or 32-bit, the FIFO allocation of the stereo channel are illustrated in Fig 22-14 to Fig 22-16. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 480: Fig 22-14 Fifo Allocation Of Stereo Channel (Sample Bit = 16-Bit)

    Left channel 8'b0 Right channel 8'b0 Left channel 8'b0 Right channel Fig 22-15 FIFO allocation of stereo channel (sample bit = 24-bit) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 481: Fig 22-16 Fifo Allocation Of Stereo Channel (Sample Bit = 32-Bit)

    Right channel(C) Left channel(A) Right channel(A) Left channel(B) Right channel(B) Fig 22-17 FIFO allocation of 5.1 channel (sample bit = 16-bit) User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 482: Registers

    S memory map are listed in Table 22-2. The base address of I S is 0x4002_0000, and the total size is 1KB. User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 483: Control Register (Is_Ctl)

    1: Enable MUTE Mute function  0: Disable  1: Enable 26:23 RSVD Reserved  22:18 BURST_SIZE 5’h0_1111: Burst16  5’h0_1011: Burst12 User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 484: Tx Page Pointer Register (Is_Tx_Page_Ptr)

    This is a physical address with word-aligned limitation. RSVD Reserved 22.5.3 Rx Page Pointer Register (IS_RX_PAGE_PTR)  Name: I S Rx Page Pointer Register  Size: 32 bits User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 485: Page Size And Sample Rate Setting Register (Is_Setting)

    Name: I S Tx Interrupt Enable Register  Size: 32 bits  Address offset: 0x0010  Read/write access: read/write … RSVD User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 486: Tx Interrupt Status Register (Is_Tx_Status_Int)

    1: Interrupt pending, write ‘1’ to clear PAGEUNAVA_IP_TX3 Tx Page 3 Unavailable Interrupt Pending  0: No Interrupt  1: Interrupt pending, write ‘1’ to clear User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 487: Rx Interrupt Enable Register (Is_Rx_Mask_Int)

    0: Disable interrupt  1: Enable interrupt P3OKIE_RX Rx Page 3 OK Interrupt Enable  0: Disable interrupt  1: Enable interrupt User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 488: Rx Interrupt Status Register (Is_Rx_Status_Int)

    1: Interrupt pending, write ‘1’ to clear P0OKIP_RX Rx Page 0 OK Interrupt Pending  0: No interrupt  1: Interrupt pending, write ‘1’ to clear User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 489: Tx Page Own Bit Register (Is_Tx_Page_Ownx)

    Size: 32 bits  Address offset: 0x0040  Read/write access: read-only … VERSION_ID Name Access Reset Description 31:0 VERSION_ID 0x2016_0001 S Version ID User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 490: Abbreviations

    Electrical fast transients External Match Control, used to control the output status Electro Magnetic Compatibility Electrostatic discharge Environment sensor capacitance tracking and calibration User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 491 Match Counter, used to counter the match event Micro CPU MCU I/F Micro Control Unit Interface MCU Mode Micro Control Unit Interface Mode User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 492 Software judgement mode Timer Counter TE Mode Tear Effect Mode Timer Transient voltage suppressors UART Universal Asynchronous Receiver/Transmitter Vertical Back Porch User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
  • Page 493 Abbreviations Vertical Front Porch Video Graphics Array VSYNC Pulse Width VSYNC Vertical Synchronization User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

  • Page 494: Revision History

    Unify and normalize the technical items and expression  Modify the incorrect description  Add necessary information for registers 2018-08-31 Initial draft User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.

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