Realtek Ameba-D RTL872 D Series User Manual page 139


Address offset: for x = 0 to 7:

LLP0 – 0x010

LLP1 – 0x068

LLP2 – 0x0c0

LLP3 – 0x118

LLP4 – 0x170

LLP5 – 0x1c8

LLP6 – 0x220

LLP7 – 0x278

Read/write access: read/write
This register does not exist if the DMAH_CHx_HC_LLP configuration parameter is set to True.
Note: You need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the channel if block chaining is
enabled – rows 6 to 10 of Table 9-19.
If DMAH_RETURN_ERR_RESP is set to True, the DMAC returns an ERROR response to an illegal register access, which includes accessing registers
that have been removed during DMAC configuration. If DMAH_RETURN_ERR_RESP is set to False, DMAC always returns an OK response.
Bit Name Access
63:32 RSVD N/A
31:2 LOC R/W
1:0 LMS R/W
The LLP register has two functions:

The logical result of the equation LLP.LOC != 0 is used to set up the type of DMA transfer—single or multi-block. Table 9-19 shows how the
method of updating the channel registers is a function of LLP.LOC != 0. If LLP.LOC is set to 0x0, then transfers using linked lists are not
enabled. This register must be programmed prior to enabling the channel in order to set up the transfer type.

LLP.LOC != 0 contains the pointer to the next LLI for block chaining using linked lists. The LLPx register can also point to the address where
write-back of the control and source/destination status information occur after block completion.
9.3.2.2.5 CTLx

Name: Control Register for Channel x

Size: 64 bits

Address offset: for x = 0 to 7:

CTL0 – 0x018

CTL1 – 0x070

CTL2 – 0x0c8

CTL3 – 0x120

CTL4 – 0x178

CTL5 – 0x1d0

CTL6 – 0x228

CTL7 – 0x280

Read/write access: read/write
This register contains fields that control the DMA transfer.
The CTLx register is part of the block descriptor (linked list item – LLI) when block chaining is enabled. It can be varied on a block-by-block basis
within a DMA transfer when block chaining is enabled.
User Manual
Reset Description
0x0 Reserved
0x0 Starting Address in Memory of next LLI if block chaining is enabled. Note that the two LSBs of
the starting address are not stored because the address is assumed to be aligned to a 32-bit
boundary. LLI accesses are always 32-bit accesses (Hsize = 2) aligned to 32-bit boundaries and
cannot be changed or programmed to anything other than 32- bit.
0x0 List Master Select. Identifies the AHB layer/interface where the memory device that stores
the next linked list item resides. 00 = AHB master 1 01 = AHB master 2 10 = AHB master 3 11 =
AHB master 4 This field does not exist if the configuration parameter DMAH_CHx_LMS is not
set to NO_HARDCODE. In this case, the read-back value is always the hardcoded value.
The maximum value of this field that can be read back is DMAH_NUM_MASTER_INT – 1.
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Direct Memory Access Controller (DMAC)
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