Realtek Ameba-D RTL872 D Series User Manual page 13

List of Tables
Fig 9-23 Channel FIFO contents at times indicated in Fig 9-22 ........................................................................................................ 107
Fig 9-24 Breakdown of block transfer .............................................................................................................................................. 108
Fig 9-25 Source FIFO contents at time indicated in Fig 9-24............................................................................................................ 109
Fig 9-26 Source FIFO contents where watermark level is dynamically adjusted ............................................................................. 109
Fig 9-27 Block transfer to destination .............................................................................................................................................. 110
Fig 9-28 Block transfer up to time 't4' ............................................................................................................................................. 112
Fig 9-29 Source, DMAC channel and destination FIFOs at time 't4' in Fig 9-26 ............................................................................... 112
Fig 9-30 FIFO status after early-terminated burst ........................................................................................................................... 113
Fig 9-31 Data loss when pre-fetching is enabled ............................................................................................................................. 114
Fig 9-32 Timing exception on dma_finish to source peripheral ...................................................................................................... 115
Fig 9-33 Case of no data loss when pre-fetching is enabled ............................................................................................................ 116
Fig 9-34 Source enters single transaction region when destination asserts dma_last[1] ............................................................... 117
Fig 9-35 Case where source does not enter single transaction region when destination asserts dma_last[1] ............................... 117
Fig 9-36 Data loss when data pre-fetching is disabled..................................................................................................................... 119
Fig 9-37 Transaction request through peripheral interrupt............................................................................................................. 120
Fig 9-38 Flow control configurations ............................................................................................................................................... 121
Fig 9-39 Case 1 watermark levels where SSI.DMATDLR = 2 ............................................................................................................. 122
Fig 9-40 Case 2 watermark levels where SSI.DMATDLR = 6 ............................................................................................................. 123
Fig 9-41 SSI receive FIFO .................................................................................................................................................................. 124
Fig 9-42 Arbitration flow for master bus interface .......................................................................................................................... 127
Fig 9-43 Example of destination scatter transfer ............................................................................................................................. 129
Fig 9-44 Source gather when SGR.SGI = 0x1 .................................................................................................................................... 129
Fig 9-45 Multi-block transfer using linked lists when DMAH_CHx_STAT_SRC set to true ............................................................... 172
Fig 9-46 Multi-block transfer using linked lists when DMAH_CHx_STAT_SRC set to false .............................................................. 173
Fig 9-47 Mapping of block descriptor (LLI) in memory to channel registers when DMAH_CHx_STAT_SRC set to true .................. 173
Fig 9-48 Mapping of block descriptor (LLI) in memory to channel registers when DMAH_CHx_STAT_SRC set to false ................. 173
Fig 9-49 Flowchart for DMA programming example ....................................................................................................................... 177
Fig 9-50 Multi-block with linked address for source and destination .............................................................................................. 181
Fig 9-51 Multi-block with linked address for source and destination where SARx and DARx between successive blocks are
contiguous .............................................................................................................................................................................. 181
Fig 9-52 DMA transfer flow for source and destination linked list address ..................................................................................... 182
Fig 9-53 Multi-block DMA transfer with source and destination address auto-reloaded ............................................................... 183
Fig 9-54 DMA transfer flow for source and destination address auto-reloaded ............................................................................. 184
Fig 9-55 Multi-block DMA transfer with source address auto-reloaded and linked list destination address ................................. 186
Fig 9-56 DMA transfer flow for source address auto-reloaded and linked list destination address ............................................... 187
Fig 9-57 Multi-block DMA transfer with source address auto-reloaded and contiguous destination address ............................... 189
Fig 9-58 DMA transfer flow for source address auto-reloaded and contiguous destination address ............................................. 189
Fig 9-59 Multi-block DMA transfer with linked list source address and contiguous destination address ....................................... 191
Fig 9-60 DMA transfer flow for source address auto-reloaded and contiguous destination address ............................................. 192
Fig 10-1 Block diagram ..................................................................................................................................................................... 194
Fig 10-2 TIM4 block diagram ............................................................................................................................................................ 196
Fig 10-3 Statistic pulse width mode diagram (positive edge of TRGI is active for capture) ............................................................. 197
Fig 10-4 Statistic pulse number mode diagram (positive edge of TRGI is active for capture, ARR=E6) ........................................... 198
Fig 10-5 PWM timer block diagram ................................................................................................................................................. 199
Fig 10-6 Counter timing diagram with prescaler division change from 1 to 2 ................................................................................. 200
Fig 10-7 Counter timing diagram with prescaler division change from 1 to 4 ................................................................................. 201
Fig 10-8 Counter timing diagram (internal clock divided by 1) ........................................................................................................ 202
Fig 10-9 Counter timing diagram (internal clock divided by 2) ........................................................................................................ 202
Fig 10-10 Counter timing diagram (internal clock divided by 4) ...................................................................................................... 202
Fig 10-11 Counter timing diagram (internal clock divided by N) ..................................................................................................... 203
Fig 10-12 Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) ......................................................... 203
Fig 10-13 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) ............................................................... 204
Fig 10-14 Edge-aligned PWM waveforms (ARR=8, CCxP=0) ............................................................................................................ 205
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